ZHCSLD2E may 2020 – july 2023 UCC28782
PRODUCTION DATA
- 1
- 1 特性
- 2 應用
- 3 描述
- 4 Revision History
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Detailed Pin Description
- 8.3.1 BUR Pin (Programmable Burst Mode)
- 8.3.2 FB Pin (Feedback Pin)
- 8.3.3 REF Pin (Internal 5-V Bias)
- 8.3.4 VDD Pin (Device Bias Supply)
- 8.3.5 P13 and SWS Pins
- 8.3.6 S13 Pin
- 8.3.7 IPC Pin (Intelligent Power Control Pin)
- 8.3.8 RUN Pin (Driver and Bias Source for Isolator)
- 8.3.9 PWMH and AGND Pins
- 8.3.10 PWML and PGND Pins
- 8.3.11 SET Pin
- 8.3.12 RTZ Pin (Sets Delay for Transition Time to Zero)
- 8.3.13 RDM Pin (Sets Synthesized Demagnetization Time for ZVS Tuning)
- 8.3.14 BIN, BSW, and BGND Pins
- 8.3.15 XCD Pin
- 8.3.16 CS, VS, and FLT Pins
- 8.4
Device Functional Modes
- 8.4.1 Adaptive ZVS Control with Auto-Tuning
- 8.4.2 Dead-Time Optimization
- 8.4.3 EMI Dither and Dither Fading Function
- 8.4.4 Control Law across Entire Load Range
- 8.4.5 Adaptive Amplitude Modulation (AAM)
- 8.4.6 Adaptive Burst Mode (ABM)
- 8.4.7 Low Power Mode (LPM)
- 8.4.8 First Standby Power Mode (SBP1)
- 8.4.9 Second Standby Power Mode (SBP2)
- 8.4.10 Startup Sequence
- 8.4.11 Survival Mode of VDD (INT_STOP)
- 8.4.12 Capacitor Voltage Balancing Function
- 8.4.13 Device Functional Modes for Bias Regulator Control
- 8.4.14
System Fault Protections
- 8.4.14.1 Brown-In and Brown-Out
- 8.4.14.2 Output Over-Voltage Protection (OVP)
- 8.4.14.3 Input Over Voltage Protection (IOVP)
- 8.4.14.4 Over-Temperature Protection (OTP) on FLT Pin
- 8.4.14.5 Over-Temperature Protection (OTP) on CS Pin
- 8.4.14.6 Programmable Over-Power Protection (OPP)
- 8.4.14.7 Peak Power Limit (PPL)
- 8.4.14.8 Output Short-Circuit Protection (SCP)
- 8.4.14.9 Over-Current Protection (OCP)
- 8.4.14.10 External Shutdown
- 8.4.14.11 Internal Thermal Shutdown
- 8.4.15 Pin Open/Short Protections
-
9 Application and Implementation
- 9.1 Application Information
- 9.2
Typical Application Circuit
- 9.2.1 Design Requirements for a 65-W USB-PD Adapter Application
- 9.2.2
Detailed Design Procedure
- 9.2.2.1 Input Bulk Capacitance and Minimum Bulk Voltage
- 9.2.2.2 Transformer Calculations
- 9.2.2.3 Clamp Capacitor Calculation
- 9.2.2.4 Bleed-Resistor Calculation
- 9.2.2.5 Output Filter Calculation
- 9.2.2.6 Calculation of ZVS Sensing Network
- 9.2.2.7 Calculation of BUR Pin Resistances
- 9.2.2.8 Calculation of Compensation Network
- 9.2.3 Application Curves
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
8.4.14.5 Over-Temperature Protection (OTP) on CS Pin
In case the FLT pin is already used for the input OVP sensing, UCC28782 provides the third and fourth OTP functions on the CS pin. The two configurations do not affect the current sense signal on the CS pin and the OPP level, because the two sensing circuits are only biased after PWML is off. Figure 8-42 shows the two application circuits. For the third OTP configuration, when the PWMH pin is pulled high, RNTC and ROPP form a resistor divider to create a temperature-dependent voltage signal on the CS pin. When the voltage exceeds the 1.2-V threshold sampled before the end of the demagnetization time (TDM) for two successive cycles, the OTP fault will be triggered. The OTP sensing circuit will not affect the operation of the peak current loop, since the PWMH is pulled low in the PWML on time duration. For auto-recovery mode, the long 1.5-s timer starts and the controller stays in fault state without switching. This long recovery time provides a temperature hysteresis to help the hot-spot temperature cool down before the next VO restart attempt. Compared with the first OTP configuration on the FLT pin, this configuration allows the OTP armed in both AAM and ABM, so the OTP can still be triggered at around 25% output load.
The fourth configuration with a small-signal PMOS is the most comprehensive way to cover a wide output load range. The RUN pin is used to bias the sensing circuit, and the PMOS gate is controlled by the PWML pin to only allow the detection to occur when PWML is low.
Figure 8-42 Two Connections to Implement OTP on the CS Pin