As the load current reduces to I_O(BUR) where V_CS reaches the V_CST(BUR) threshold, the control mode transitions to ABM starts and V_CS is clamped. The peak magnetizing current and the switching frequency (f_SW) of each switching cycle are fixed for a given input voltage level. V_CST(BUR) is programmed by the BUR pin voltage (V_BUR). The PWM pattern of ABM is shown in Figure 7-31. When RUN goes high, a delay time between RUN and PWML (t_D(RUN-PWML)) is given to allow both the gate driver and the UCC28781-Q1 controller time to wake up from a wait state to a run state. The first PWML pulse turns on Q_L close to a valley point of the DCM ringing on the switch-node voltage (V_SW) by sensing the condition of zero crossing detection (ZCD) on the auxiliary winding voltage (V_AUX).

The following switching cycles operate in a ZVS condition, since PWMH is enabled. As the number of PWML pulses (N_SW) in the burst packet reaches its target value, the RUN pin pulls low after the ZCD of the last switching cycle is detected, and forces the isolated gate driver and controller into a wait state for the quiescent current reduction of both devices. In this mode, the minimum off-time of the RUN signal is 2.2 μs and the minimum on-time of PWML is limited to the leading-edge blanking time (t_CSLEB) of the peak current loop. However, more grouped pulses means more risk of higher output ripple and higher audible noise. The following equation estimates how burst frequency (f_BUR) varies with output load and other parameters.

As I_O < I_O(BUR), f_BUR can become lower than the audible noise range if N_SW is fixed. In ABM, N_SW is modulated to ensure f_BUR stays above 20 kHz by monitoring f_BUR in each burst period. As I_O decreases, f_BUR decreases and reaches a predetermined low-level frequency threshold (f_BUR(LR)) of 25 kHz. The ABM loop commands N_sw of both PWML and PWMH to be reduced by one pulse to maintain f_BUR above f_BUR(LR). At the same time, the burst frequency ripple on the output voltage reduces as N_SW drops with the load reduction. As I_O increases, f_BUR becomes higher and reaches a predetermined high-level frequency threshold (f_BUR(UP)). The ABM loop commands N_SW to be increased by one pulse to push f_BUR back below f_BUR(UP).

The maximum N_SW and the f_BUR(UP) thresholds are modified based on the output voltage condition, i.e., the positive VS-pin voltage level. When the V_VS sampled at the PWMH falling edge is less than the 2.4-V threshold (V_VSLV(LR)), the maximum N_SW is 5 pulses and the f_BUR(UP2) is 50 kHz. When the sampled V_VS is higher than the 2.5-V threshold (V_VSLV(UP)), the maximum N_SW is 9 pulses, the f_BUR(UP2) is 50 kHz for N_SW ≤ 3, and the f_BUR(UP1) is 34 kHz for N_SW> 3. The IPC-pin voltage does not affect the parameters in ABM mode.

This algorithm maximizes the number of pulses in each burst packet to improve light-load efficiency, while also limiting the burst output ripple and audible noise. As I_O is close to the boundary between AAM and ABM, the two burst packets with the maximum pulse count may start to bundle together. In order to mitigate the output ripple and audible noise concerns, when the bundled burst packet appears two times within eight sequential burst cycles, the 5-μA current sink into the BUR pin is enabled to reduce V_BUR . The less energy per cycle with a lower V_BURwill force the control loop to transition from ABM to AAM smoothly in order to allow the peak current increase to maintain the output voltage regulation.

Figure 7-31 PWM Pattern in ABM