As shown in Figure 7-36, after V_VDD reaches V_VDD(ON), an internal 13-V regulator on the P13 pin should force V_P13 back to the regulation level before PWML starts switching. If the recommended P13-pin capacitor (C_P13) of 1 μF and the connection to the depletion-mode MOSFET (Q_S) are in place, the settling time of V_P13 to 14 V is much longer than 10 μs with a limited 1.9-mA sink current of the regulator (I_P13(START)) to discharge C_P13.

The first fault scenario is that if C_P13 is too small, or the P13 pin is open, the pin is not able to control Q_S correctly for the high-voltage sensing function of ZVS control, so no switching action will be performed. When either two situations happen, V_P13 settles to 13 V very quickly instead. Therefore, after a 10-μs delay from the instant of V_VDD reaching V_VDD(ON), UCC28781-Q1 checks if V_P13 is below 14 V for the pin-fault detection, and then performs one UVLO cycle of VDD directly without switching as the protection response.

The above protection is to prevent the controller from generating PWM signals. However, when the P13 pin is open and disconnected from the Q_S gate, the source voltage of Q_S keeps increasing. To protect the P13-pin open event, a small Zener diode (D_P13) between Q_S gate to AGND should be used to limit the Q_S source voltage. D_P13 should be higher than V_VDD(ON) , so as to prevent interference with normal VDD startup. A 20-V Zener diode is recommended.

The second fault scenario is the over-voltage condition of P13 pin after the converter starts switching. When the switch-node voltage (V_SW) rises with a high dV/dt condition, there is a charge current flowing through the junction capacitance of Q_S, and part of the current can charge up C_P13. If the overshoot is too large, the voltage on the SWS pin also increases due to the nature of depletion-mode MOSFET operation. UCC28781-Q1 detects the overshoot event on P13 pin with a 15-V over-voltage threshold cycle-by-cycle. When V_P13 is higher than 15 V for three consecutive PWML pulses, the P13 over-voltage protection is triggered which performs one UVLO cycle of VDD.

The third fault scenario is an P13 pin short event at the beginning of VDD startup, and Q_S is unable to charge up the VDD capacitor to V_DD(ON), so there is no chance to enable the controller.