Table 1. Design Example Performance Requirements

8.2.2.1 Stand-By Power Estimate

The extra-low operating frequency capability and minimal bias power of the UCC28730-Q1, in conjunction with its companion micro-power wake-up device UCC24650, allow for the achievement of less than 5-mW input stand-by power consumption under no-load conditions. This is often referred to as zero-power stand-by.

Assuming that no-load stand-by power is a critical design parameter, determine the estimated no-load input power based on the target maximum switching frequency and the maximum output power. The following equation estimates the stand-by power of the converter.

Equation 7.

For a typical flyback converter, η_SB may range between 0.5 and 0.7, but the lower factor should be used for an initial estimate. Also, f_MIN should be estimated at 3x to 4x f_SW(min) to allow for possible parameter adjustment.

If the P_STBY calculation result is well below 5 mW, there is an excellent chance of achieving zero-power stand-by in the actual converter. If the result is near 5 mW, some design adjustment to f_MAX, f_MIN, and η_SB may be needed to achieve zero-power. If the result is well above 5 mW, there is little chance to achieve zero-power at the target power level unless additional special circuitry and design effort is applied.

8.2.2.2 Input Bulk Capacitance and Minimum Bulk Voltage

Bulk capacitance may consist of one or more capacitors connected in parallel, often with some inductance between them to suppress differential-mode conducted noise. EMI filter design is beyond the scope of this procedure.

Determine the minimum voltage on the input capacitance, C_B1 and C_B2 total, in order to determine the maximum N_P to N_S turns ratio of the transformer. The input power of the converter based on target full-load efficiency, minimum input RMS voltage, and minimum AC input frequency are used to determine the input capacitance value.

Maximum input power is used in the C_BULK calculation and is determined by the V_OCV, I_OCC, and full-load efficiency targets.

Equation 8.

The below equation provides an accurate solution for input capacitance needed to achieve a minimum bulk valley voltage target V_BULK(min), accounting for hold-up during any loss of AC power for a certain number of half-cycles, N_HC, by an AC-line drop-out condition. Alternatively, if a given input capacitance value is prescribed, iterate the V_BULK(min) value until that target capacitance is obtained, which determines the V_BULK(min) expected for that capacitance.

Equation 9.

8.2.2.3 Transformer Turns Ratio, Inductance, Primary-Peak Current

The maximum primary-to-secondary turns ratio can be determined by the target maximum switching frequency at full load, the minimum input capacitor bulk voltage, and the estimated DCM quasi-resonant time.

First, determine the maximum duty cycle of the MOSFET based on the target maximum switching frequency, f_MAX, the secondary conduction duty cycle, D_MAGCC, and the DCM resonant period, t_R. For t_R, assume 2 µs (500-kHz resonant frequency), if you do not have an estimate from experience or previous designs. For the transition mode operation limit, the time interval from the end of the secondary current conduction to the first resonant valley of the V_DS voltage is ½ of the DCM resonant period, or 1 µs assuming 500 kHz. Actual designs vary. D_MAX can be determined using the equation below.

Equation 10.

D_MAGCC is defined as the secondary diode conduction duty cycle during constant current, CC, operation. In the UCC28730-Q1, it is fixed internally at 0.432. Once D_MAX is known, the ideal turns ratio of the primary-to-secondary windings can be determined with the equation below. The total voltage on the secondary winding needs to be determined, which is the total of V_OCV, the secondary rectifier drop V_F, and cable compensation voltage V_OCBC, if used. For 5-V USB charger applications, for example, a turns ratio in the range of 13 to 15 is typically used.

Equation 11.

The actual turns ratio depends on the actual number of turns on each of the transformer windings. Choosing N_PS > N_PS(ideal) results in an output power limit lower than (V_OCV x I_OCC) when operating at V_IN(min), and line-frequency ripple may appear on V_OUT. Choosing N_PS < N_PS(ideal) allows full-power regulation down to V_IN(min), but increases conduction losses and the reverse voltage stress on the output rectifier.

Once the actual turns ratio is determined from a detailed transformer design, use this ratio for the following parameter calculations.

The UCC28730-Q1 constant-current regulation is achieved by maintaining a maximum D_MAGCC duty cycle of 0.432 at the maximum primary current setting. The transformer turns ratio and constant-current regulating factor determine the current-sense resistor, R_CS, for a regulated constant-current target, I_OCC. Actual implementation of R_CS may consist of multiple parallel resistors to meet power rating and accuracy requirements.

Since not all of the energy stored in the transformer is transferred to the secondary output, a transformer efficiency term, η_XFMR, is used to account for the core and winding loss ratio, leakage inductance loss ratio, and primary bias power ratio with respect to the rated output power. At full load, an overall transformer efficiency estimate of 0.91, for example, includes ~3% leakage inductance loss, ~5% core and winding loss, and ~1% bias power. Actual loss ratios may vary from this example.

Equation 12.

The primary-transformer inductance can be calculated using the standard energy storage equation for flyback transformers. Primary current, maximum switching frequency and output and transformer power losses are included in the equation below.

Initially, determine the transformer peak primary current, I_PP(max).

Peak-primary current is simply the maximum current-sense threshold divided by the current-sense resistance.

Equation 13.

Then, calculate the primary inductance of the transformer, L_P.

Equation 14.

The auxiliary winding to secondary winding turns ratio, N_AS, is determined by the lowest target operating output voltage in constant current regulation, the VDD turn-off threshold of the UCC28730-Q1, and the forward diode drops in the respective winding networks.

Equation 15.

There is additional energy supplied to VDD from the transformer leakage inductance energy which may allow a lower turns ratio to be used in many designs.

8.2.2.4 Transformer Parameter Verification

The transformer turns ratio selected affects the MOSFET V_DS and secondary rectifier reverse voltage V_REV, these should be reviewed.

The secondary rectifier reverse voltage stress is determined by the equation below. A snubber around the rectifier may be necessary to suppress any voltage spike, due to secondary leakage inductance, which adds to V_REV.

Equation 16.

For the MOSFET V_DS peak stress, an estimated leakage inductance voltage spike, V_LK, should to be included.

Equation 17.

In the high-line, minimum-load condition, the UCC28730-Q1 requires a minimum on-time of the MOSFET (t_ON(min)) and minimum demagnetization time of the secondary rectifier (t_DMAG(min)). The selection of f_MAX, L_P and R_CS affects the actual minimum t_ON and t_DMAG achieved. The following equations are used to determine if the minimum t_ON is greater than t_CSLEB and minimum t_DMAG target of >1.2 µs is achieved.

Equation 18.

Equation 19.

8.2.2.5 Output Capacitance

With ordinary flyback converters, the output capacitance value is typically determined by the transient response requirement for a specific load step, I_TRAN, sometimes from a no-load condition. For example, in some USB charger applications, there is requirement to maintain a transient minimum V_O of 4.1 V with a load-step of 0 mA to 500 mA. Equation 20 below assumes that the switching frequency can be at the UCC28730-Q1 minimum of f_SW(min).

Equation 20.

This results in a C_OUT value of over 17,000 µF, unless a substantial pre-load is used to raise the minimum switching frequency. However, the wake-up feature allows the use of a much smaller value for C_OUT because the wake-up response immediately cancels the Wait state and provides high-frequency power cycles to recover the output voltage from the load transient. The secondary-side voltage monitor UCC24650 provides the UCC28730-Q1 with a wake-up signal when it detects a -3% droop in output voltage.

Equation 21.

where

• (dV_OUT/dt) is the slope at which the UCC24650 must detect the V_OUT droop. Use a slope factor of 3700 V/s or lower for this calculation.

The UCC28730-Q1 incorporates internal voltage-loop compensation circuits so that external compensation is not necessary, provided that the value of C_OUT is high enough. The following equation determines a minimum value of C_OUT necessary to maintain a phase margin of about 40 degrees over the full-load range. K_Co is a dimensionless factor which has a value of 100.

Equation 22.

Another consideration for selecting the output capacitor(s) is the maximum ripple voltage requirement, V_RIPPLE(max), which is reviewed based on the maximum output load, the secondary-peak current, and the equivalent series resistance (ESR) of the capacitor. The two major contributors to the output ripple voltage are the change in V_OUT due to the charge and discharge of C_OUT between each switching cycle and the step in V_OUT due to the ESR of C_OUT. TI recommends an initial allocation of 33% of V_RIPPLE(max) to ESR, 33% to C_OUT, and the remaining 33% to account for additional low-level ripple from EMI-dithering, valley-hopping, sampling noise and other random contributors. In Equation 23, a margin of 50% is applied to the capacitor ESR requirement to allow for aging. In Equation 24, set ΔV_CQ = 0.33 x V_RIPPLE(max) to determine the minimum value of C_OUT with regard to ripple voltage limitation. If other allocations of the allowable ripple voltage are desired, these equations may be adjusted accordingly.

Equation 23.

Equation 24.

Choose the largest value of the previous C_OUT calculations for the minimum output capacitance. If the value of C_OUT becomes excessive to meet a stringent ripple limitation, a C-L-C pi-filter arrangement can be considered to as an alternative to a simple capacitor-only filter. This arrangement is beyond the scope of this datasheet.

8.2.2.6 VDD Capacitance, C_VDD

A capacitor is required on VDD to provide:

1. Run-state bias current during start-up while VDD falls toward UVLO, until V_OCC is reached,
2. Wait-state bias current between steady-state low-frequency power cycles and
3. Wait-state bias current between minimum-frequency power cycles while V_OUT recovers from a transient overshoot.

Generally, the value to satisfy (3) also satisfies (2) and (1), however the value for (1) may be the largest if the converter must provide high output current at a voltage below V_OCC during power up.

The capacitance on VDD needs to supply the device operating current until the output of the converter reaches the target minimum operating voltage in constant-current regulation, V_OCC. At that point, the auxiliary winding can sustain the bias voltage to the UCC28730-Q1 above the UVLO shutdown threshold. The total current available to charge the output capacitors and supply an output load and is the constant-current regulation target, I_OCC.

Equation 25 assumes that all of the output current of the flyback is available to charge the output capacitance until the minimum output voltage is achieved. For margin, there is an estimated 1 mA of average gate-drive current added to the run current and 1 V added to the minimum VDD.

Equation 25.

At light loads, the UCC28730-Q1 enters a Wait-state between power cycles to minimize bias power and improve efficiency. Equation 26 estimates the minimum capacitance needed to obtain a target maximum ripple voltage on VDD (V_VDD(maxΔ) < 1 V, for example) during the Wait state, which occurs at the lowest possible switching frequency.

Equation 26.

Choose the largest value of the previous C_VDD calculations for the minimum VDD capacitance.

8.2.2.7 VS Resistor Divider, Line Compensation, and Cable Compensation

The VS divider resistors determine the output voltage regulation point of the flyback converter. Also, the high-side divider resistor, R_S1, determines the line voltage at which the controller enables continuous DRV operation. R_S1 is initially determined based on the transformer primary to auxiliary turns ratio and the desired input voltage operating threshold.

Equation 27.

The low-side VS divider resistor, R_S2, is selected based on the desired constant-voltage output regulation target, V_OCV.

Equation 28.

The UCC28730-Q1 can maintain tight constant-current regulation over input line by utilizing the line compensation feature. The line compensation resistor value, R_LC, is determined by various system parameters and the combined gate-drive turn-off and MOSFET turn-off delays, t_D. Assume a 50-ns internal propagation delay in the UCC28730-Q1.

Equation 29.

The UCC28730-Q1 provides adjustable cable compensation of up to approximately +8% of V_OCV by connecting a resistor between the CBC terminal and GND. This compensation voltage, V_OCBC, represents the incremental increase in voltage, above the nominal no-load output voltage, needed to cancel or reduce the incremental decrease in voltage at the end of a cable due to its resistance. The programming resistance required for the desired cable compensation level at the converter output terminals can be determined using the equation below. As the load current changes, the cable compensation voltage also changes slowly to avoid disrupting control of the main output voltage. A sudden change in load current will induce a step change of output voltage at the end of the cable until the compensation voltage adjusts to the required level. Note that the cable compensation does not change the overvoltage protection (OVP) threshold,V_OVP (see Electrical Characteristics), so the operating margin to OVP is less when cable compensation is used. If cable compensation is not required, CBC may remain unconnected.

Equation 30.

8.2.2.8 VS Wake-Up Detection

The amplitude of the wake-up signal at the VS input must be high enough to be detected. This signal, which originates on the secondary winding, is limited by the impedances of the wake-up signal driver and the L-C resonant tank of the transformer windings. The signal is further attenuated by the VS divider resistors. To maximize the wake-up signal amplitude, the pulse width, t_WAKE, of the wake-up signal should be at least 1/4-wavelength of the switched-node resonant frequency, f_RES. The resonant frequency depends on the primary magnetizing inductance and the total equivalent capacitance at the switching node, that is, the primary-side MOSFET drain node. The switched-node capacitance, C_SWN, includes the MOSFET C_OSS, the transformer winding capacitance, and all other stray circuit capacitance attached to the MOSFET drain. Use Equation 31 to determine f_RES. Conversely, if f_RES is known by experience or measurement, C_SWN can be derived from Equation 31.

Equation 31.

Since the wake-up pulse width is typically fixed by the driver device, such as the UCC24650, maximum signal strength is obtained when Equation 32 is true. Since L_P is generally fixed by other system requirements, only C_SWN can be reduced to increase f_RES, if necessary.

Equation 32.

Equation 33 is used to ensure that there is sufficient amplitude at the VS input to reliably trigger the wake-up function, where R_{WAKE_TOT} is the total secondary-side resistance of the wake-up signal driver and any series resistance. An over-drive of 15 mV is added to the wake-up threshold level for margin.

Equation 33.