ZHCSGD9 June 2017 UCC28730-Q1
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3 Feature Description
- 7.4 Device Functional Modes
-
8 Application and Implementation
- 8.1 Application Information
- 8.2
Typical Application
- 8.2.1 Design Requirements
- 8.2.2
Detailed Design Procedure
- 8.2.2.1 Stand-By Power Estimate
- 8.2.2.2 Input Bulk Capacitance and Minimum Bulk Voltage
- 8.2.2.3 Transformer Turns Ratio, Inductance, Primary-Peak Current
- 8.2.2.4 Transformer Parameter Verification
- 8.2.2.5 Output Capacitance
- 8.2.2.6 VDD Capacitance, CVDD
- 8.2.2.7 VS Resistor Divider, Line Compensation, and Cable Compensation
- 8.2.2.8 VS Wake-Up Detection
- 8.2.3 Application Curves
- 8.3 Do's and Don'ts
- 9 Power Supply Recommendations
- 10Layout
-
11器件和文檔支持
- 11.1
器件支持
- 11.1.1
器件命名規(guī)則
- 11.1.1.1 電容術(shù)語（以法拉為單位）
- 11.1.1.2 占空比相關(guān)術(shù)語
- 11.1.1.3 頻率術(shù)語（以赫茲為單位）
- 11.1.1.4 電流術(shù)語（以安培為單位）
- 11.1.1.5 電流和電壓調(diào)節(jié)術(shù)語
- 11.1.1.6 變壓器術(shù)語
- 11.1.1.7 功率術(shù)語（以瓦特為單位）
- 11.1.1.8 電阻術(shù)語（以 Ω 為單位）
- 11.1.1.9 時(shí)序術(shù)語（以秒為單位）
- 11.1.1.10 直流電壓術(shù)語（以伏特為單位）
- 11.1.1.11 交流電壓術(shù)語（以伏特為單位）
- 11.1.1.12 效率術(shù)語
- 11.1.1
器件命名規(guī)則
- 11.2 文檔支持
- 11.3 接收文檔更新通知
- 11.4 社區(qū)資源
- 11.5 商標(biāo)
- 11.6 靜電放電警告
- 11.7 Glossary
- 11.1
器件支持
- 12機(jī)械、封裝和可訂購信息
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- D|7
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
訂購信息
10 Layout
10.1 Layout Guidelines
In order to increase the reliability and feasibility of the project it is recommended to adhere to the following guidelines for PCB layout.
- Minimize stray capacitance on the VS node. Place the voltage sense resistors (RS1 and RS2 in Figure 24 through Figure 27) close to the VS pin.
- TI recommends to connect the HV input to a non-switching source of high voltage, not to the MOSFET drain, to avoid injecting high-frequency capacitive current pulses into the device.
- Arrange the components to minimize the loop areas of the switching currents as much as possible. These areas include such loops as the transformer primary winding current loop, the MOSFET gate-drive loop, the primary snubber loop, the auxiliary winding loop and the secondary output current loop.
10.2 Layout Example
The partial layout example of Figure 28 demonstrates an effective component and track arrangement for low-noise operation on a single-layer printed circuit board. Actual board layout must conform to the constraints on a specific design, so many variations are possible.
Figure 28. UCC28730-Q1 Partial Layout Example