ZHCSQE6 October 2023 UCC27332-Q1
PRODUCTION DATA
- 1
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Detailed Description
- 8 Applications and Implementation
- 9 Device and Documentation Support
- 10Mechanical, Packaging, and Orderable Information
7.3.1 VDD Power On Reset
The UCC27332-Q1 device offers an power on reset lockout threshold of 3.0 V (rising). The device's hysteresis range helps to avoid any chattering due to the presence of noise on the bias supply. 0.3 V of typical POR hysteresis is expected for 4-V devices. There is no significant driver output turnon delay due to the POR feature. The POR turn-off delay is also minimized as much as possible. The POR delay is designed to minimize chattering that may occur due to very fast transients that may appear on VDD. When the bias supply is below POR thresholds, the outputs are held actively low irrespective of the state of input pins and enable pin. The device accepts a wide range of slew rates on its VDD pin.
Figure 7-1 Power Up