ZHCSKA3D September 2019 – November 2023 UCC21750-Q1
PRODUCTION DATA
- 1
- 1 特性
- 2 應(yīng)用
- 3 說(shuō)明
- 4 Revision History
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Power Ratings
- 6.6 Insulation Specifications
- 6.7 Safety Limiting Values
- 6.8 Electrical Characteristics
- 6.9 Safety-Related Certifications
- 6.10 Switching Characteristics
- 6.11 Insulation Characteristics Curves
- 6.12 Typical Characteristics
- 7 Parameter Measurement Information
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 Power Supply
- 8.3.2 Driver Stage
- 8.3.3 VCC and VDD Undervoltage Lockout (UVLO)
- 8.3.4 Active Pulldown
- 8.3.5 Short Circuit Clamping
- 8.3.6 Internal Active Miller Clamp
- 8.3.7 Desaturation (DESAT) Protection
- 8.3.8 Soft Turn-Off
- 8.3.9 Fault (FLT, Reset, and Enable (RST/EN)
- 8.3.10 Isolated Analog to PWM Signal Function
- 8.4 Device Functional Modes
-
9 Applications and Implementation
- 9.1 Application Information
- 9.2
Typical Application
- 9.2.1 Design Requirements
- 9.2.2
Detailed Design Procedure
- 9.2.2.1 Input Filters for IN+, IN–, and RST/EN
- 9.2.2.2 PWM Interlock of IN+ and IN–
- 9.2.2.3 FLT, RDY, and RST/EN Pin Circuitry
- 9.2.2.4 RST/EN Pin Control
- 9.2.2.5 Turn-On and Turn-Off Gate Resistors
- 9.2.2.6 Overcurrent and Short Circuit Protection
- 9.2.2.7 Isolated Analog Signal Sensing
- 9.2.2.8 Higher Output Current Using an External Current Buffer
- 9.2.3 Application Curves
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- DW|16
散熱焊盤(pán)機(jī)械數(shù)據(jù) (封裝 | 引腳)
- DW|16
訂購(gòu)信息
7.1.1 Regular Turn-OFF
Figure 7-1 shows the propagation delay measurement for non-inverting configurations. Figure 7-2 shows the propagation delay measurement with the inverting configurations.
Figure 7-1 Non-inverting Logic Propagation Delay Measurement
Figure 7-2 Inverting
Logic Propagation Delay Measurement