External active miller clamp feature allows the gate driver to stay at the low status when the gate voltage is detected below V_CLMPTH. When the other switch of the phase leg turns on, the dV/dt can cause a current through the parasitic miller capacitance of the switch and sink in the gate driver. The sinking current causes a negative voltage drop on the turn off gate resistance, and bumps up the gate voltage to cause a false turn on. The external active miller clamp features allows flexibility of board layout and active miller clamp pulldown strength. Limited by the board layout, if the driver cannot be placed close enough to the switch, external active miller clamp MOSFET can be placed close to the switch and the MOSFET can be chosen according to the peak current needed. Caution must be exercised when the driver is place far from the power semiconductor. Since the device has high peak sink and source current, the high dI/dt in the gate loop can cause a ground bounce on the board parasitics. The ground bounce can cause a positive voltage bump on CLMPE pin during the turn off transient, and results in the external active miller clamp MOSFET to turn on shortly and add extra drive strength to the sink current. To reduce the ground bounce, a 2-? resistance is recommended to the gate of the external active clamp MOSFET.

When the V_OUTH is detected to be lower than V_CLMPTH above VEE, the CLMPE pin outputs a 5-V voltage with respect to VEE, the external clamp FET is in linear region and the pulldown current is determined by the peak drain current, unless the on-resistance of the external clamp FET is large.

Equation 9.

Where

• I_{D_PK} is the peak drain current of the external clamp FET
• V_DS is the drain-to-source voltage of the clamp FET when the CLMPE is activated
• R_{DS_ON} is the on-resistance of the external clamp FET

The total delay time of the active miller clamp circuit from the gate voltage detection threshold V_CLMPTH can be calculated as t_DCLMPE+t_CLMPER. t_CLMPER depends on the parameter of the external active miller clamp MOSFET. As long as the total delay time is longer than the deadtime of high-side and low-side switches, the driver can effectively protect the switch from false turn on issue caused by miller effect.

Figure 8-7 External Active Miller Clamp Configuration