ZHCSFN1A November 2016 – January 2022 UCC20520
PRODUCTION DATA
The input pins (PWM and DIS) of UCC20520 are based on a TTL and CMOS compatible input-threshold logic that is totally isolated from the VDD supply voltage. The input pins are easy to drive with logic-level control signals (Such as those from 3.3-V micro-controllers), since UCC20520 has a typical high threshold (VPWMH) of 1.8 V and a typical low threshold of 1 V, which vary little with temperature (see Figure 6-20,Figure 6-21). A wide hysteresis (VPWM_HYS) of 0.8 V makes for good noise immunity and stable operation. If any of the inputs are ever left open, internal pull-down resistors force the pin low. These resistors are typically 200 kΩ (See Section 8.2). However, it is still recommended to ground an input if it is not being used.
Since the input side of UCC20520 is isolated from the output drivers, the input signal amplitude can be larger or smaller than VDD, provided that it doesn’t exceed the recommended limit. This allows greater flexibility when integrating with control signal sources, and allows the user to choose the most efficient VDD for their chosen gate. That said, the amplitude of any signal applied to PWM must never be at a voltage higher than VCCI.