ZHCSFN1A November 2016 – January 2022 UCC20520
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Power Ratings
- 6.6 Insulation Specifications
- 6.7 Safety-Related Certifications
- 6.8 Safety-Limiting Values
- 6.9 Electrical Characteristics
- 6.10 Switching Characteristics
- 6.11 Insulation Characteristics Curves
- 6.12 Typical Characteristics
- 7 Parameter Measurement Information
- 8 Detailed Description
-
9 Application and Implementation
- 9.1 Application Information
- 9.2
Typical Application
- 9.2.1 Design Requirements
- 9.2.2
Detailed Design Procedure
- 9.2.2.1 Designing PWM Input Filter
- 9.2.2.2 Select External Bootstrap Diode and its Series Resistor
- 9.2.2.3 Gate Driver Output Resistor
- 9.2.2.4 Estimate Gate Driver Power Loss
- 9.2.2.5 Estimating Junction Temperature
- 9.2.2.6 Selecting VCCI, VDDA/B Capacitor
- 9.2.2.7 Dead Time Setting Guidelines
- 9.2.2.8 Application Circuits with Output Stage Negative Bias
- 9.2.2.9 56
- 9.2.3 Application Curves
- 10Layout
- 11Device and Documentation Support
10.2 Layout Example
Figure 10-1 shows a 2-layer PCB layout example with the signals and key components labeled.
Figure 10-1 Layout ExampleFigure 10-2 and Figure 10-3 shows top and bottom layer traces and copper.
There are no PCB traces or copper between the primary and secondary side, which ensures isolation performance.
PCB traces between the high-side and low-side gate drivers in the output stage are increased to maximize the creepage distance for high-voltage operation, which will also minimize cross-talk between the switching node VSSA (SW), where high dv/dt may exist, and the low-side gate drive due to the parasitic capacitance coupling.
Figure 10-2 Top Layer Traces and Copper
Figure 10-3 Bottom Layer Traces and CopperFigure 10-4 and Figure 10-5 are 3D layout pictures with top view and bottom views.
The location of the PCB cutout between the primary side and secondary sides, which ensures isolation performance.
Figure 10-4 3-D PCB Top View
Figure 10-5 3-D PCB Bottom View