ZHCSDY5C July 2015 – July 2024 TUSB4041I-Q1
PRODUCTION DATA
- 1
- 1 特性
- 2 應用
- 3 說明
- 4 Pin Configuration and Functions
- 5 Specifications
- 6 Detailed Description
-
7 Application and Implementation
- 7.1 Application Information
- 7.2
Typical Application
- 7.2.1 Design Requirements
- 7.2.2
Detailed Design Procedure
- 7.2.2.1 Upstream Port Implementation
- 7.2.2.2 Downstream Port 1 Implementation
- 7.2.2.3 Downstream Port 2 Implementation
- 7.2.2.4 Downstream Port 3 Implementation
- 7.2.2.5 Downstream Port 4 Implementation
- 7.2.2.6 VBUS Power Switch Implementation
- 7.2.2.7 Clock, Reset, and Miscellaneous
- 7.2.2.8 TUSB4041I-Q1 Power Implementation
- 7.2.3 Application Curves
- 7.3 Power Supply Recommendations
- 7.4 Layout
-
8 Register Maps
- 8.1 Configuration Registers
- 8.2 ROM Signature Register
- 8.3 Vendor ID LSB Register
- 8.4 Vendor ID MSB Register
- 8.5 Product ID LSB Register
- 8.6 Product ID MSB Register
- 8.7 Device Configuration Register
- 8.8 Battery Charging Support Register
- 8.9 Device Removable Configuration Register
- 8.10 Port Used Configuration Register
- 8.11 Device Configuration Register 2
- 8.12 USB 2.0 Port Polarity Control Register
- 8.13 UUID Byte N Register
- 8.14 Language ID LSB Register
- 8.15 Language ID MSB Register
- 8.16 Serial Number String Length Register
- 8.17 Manufacturer String Length Register
- 8.18 Product String Length Register
- 8.19 Serial Number String Registers
- 8.20 Manufacturer String Registers
- 8.21 Product String Byte N Register
- 8.22 Additional Feature Configuration Register
- 8.23 Device Status and Command Register
- 9 Device and Documentation Support
- 10Revision History
- 11Mechanical, Packaging, and Orderable Information
6.3.4 Clock Generation
The TUSB4041I-Q1 device accepts a crystal input to drive an internal oscillator or an external clock source. If a clock is provided to the XI pin instead of a crystal, the XO pin is left open. Otherwise, if a crystal is used, the connection must follow these guidelines. Because the XI and XO pins are coupled to other leads and supplies on the PCB, keep traces as short as possible and away from any switching leads. Minimize the capacitance between the XI and XO pins by shielding C1 and C2 with the clean ground lines.
Figure 6-1 TUSB4041I-Q1 Clock