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ZHCS904I May 2012 – March 2017 TRF7964A

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

RHB|32
- MPQF130D

散熱焊盤機械數據 (封裝 | 引腳)

RHB|32
- QFND029X

訂購信息

5 Specifications

5.1 Absolute Maximum Ratings⁽¹⁾ ⁽²⁾

over operating free-air temperature range (unless otherwise noted)

			MIN	MAX	UNIT
V_IN	Input voltage range		–0.3	6	V
I_IN	Maximum current V_IN			150	mA
T_J	Maximum operating virtual junction temperature	Any condition		140	°C
T_J	Maximum operating virtual junction temperature	Continuous operation, long-term reliability⁽³⁾		125	°C
T_STG	Storage temperature		–55	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions are not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to substrate ground terminal V_SS.

(3) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may result in reduced reliability or lifetime of the device.

5.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	±2000	V
		Charged-device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾	±500	V
		Machine model (MM)	±200	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±2000 V may actually have higher performance.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±500 V may actually have higher performance.

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

			MIN	TYP	MAX	UNIT
V_IN	Operating input voltage		2.7	5	5.5	V
T_A	Operating ambient temperature		–40	25	110	°C
T_J	Operating virtual junction temperature		–40	25	125	°C
V_IL	Input voltage, logic low	I/O lines, IRQ, SYS_CLK, DATA_CLK, EN, EN2, ASK/OOK, MOD			0.2 × V_{DD_I/O}	V
V_IH	Input voltage threshold, logic high	I/O lines, IRQ, SYS_CLK, DATA_CLK, EN, EN2, ASK/OOK, MOD	0.8 × V_{DD_I/O}			V

5.4 Electrical Characteristics

TYP operating conditions are T_A = 25°C, VIN = 5 V, full-power mode (unless otherwise noted)
MIN and MAX operating conditions are over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_OL	Low-level output voltage			0.2 × V_{DD_I/O}		V
V_OH	High-level output voltage			0.8 × V_{DD_I/O}		V
I_PD1	Supply current in power down mode 1	All building blocks disabled, including supply-voltage regulators; measured after 500-ms settling time (EN = 0, EN2 = 0)		0.5	5	µA
I_PD2	Supply current in power down mode 2 (sleep mode)	The SYS_CLK generator and V_{DD_X} remain active to support external circuitry; measured after 100-ms settling time (EN = 0, EN2 = 1)		120	200	µA
I_STBY	Supply current in stand-by mode	Oscillator running, supply-voltage regulators in low-consumption mode (EN = 1, EN2 = x)		1.9	3.5	mA
I_ON1	Supply current without antenna driver current	Oscillator, regulators, RX and AGC active, TX is off		10.5	14	mA
I_ON2	Supply current, TX (half power)	Oscillator, regulators, RX and AGC and TX active, P_OUT = 100 mW		70	78	mA
I_ON3	Supply current, TX (full power)	Oscillator, regulators, RX and AGC and TX active, P_OUT = 200 mW		130	150	mA
V_POR	Power-on-reset voltage	Input voltage at V_IN	1.4	2	2.6	V
V_BG	Bandgap voltage (pin 11)	Internal analog reference voltage	1.5	1.6	1.7	V
V_{DD_A}	Regulated output voltage for analog circuitry (pin 1)	V_IN = 5 V	3.1	3.4	3.8	V
V_{DD_X}	Regulated supply for external circuitry	Output voltage pin 32, V_IN = 5 V	3.1	3.4	3.8	V
I_{VDD_Xmax}	Maximum output current of V_{DD_X}	Output current pin 32, V_IN = 5 V			20	mA
R_RFOUT	Antenna driver output resistance ⁽³⁾	Half-power mode, V_IN = 2.7 V to 5.5 V		8	12	Ω
R_RFOUT	Antenna driver output resistance ⁽³⁾	Full-power mode, V_IN = 2.7 V to 5.5 V		4	6	Ω
R_RFIN	RX_IN1 and RX_IN2 input resistance		4	10	20	kΩ
V_{RF_INmax}	Maximum RF input voltage at RX_IN1 and RX_IN2	V_{RF_INmax} should not exceed V_IN		3.5		V_pp
V_{RF_INmin}	Minimum RF input voltage at RX_IN1 and RX_IN2 (input sensitivity)⁽¹⁾	f_SUBCARRIER = 424 kHz		1.4	2.5	mV_pp
V_{RF_INmin}		f_SUBCARRIER = 848 kHz		2.1	3	mV_pp
f_{SYS_CLK}	SYS_CLK frequency	In power mode 2, EN = 0, EN2 = 1	25	60	120	kHz
f_C	Carrier frequency	Defined by external crystal		13.56		MHz
t_CRYSTAL	Crystal run-in time	Time until oscillator stable bit is set (register 0x0F)⁽²⁾		3		ms
f_{D_CLKmax}	Maximum DATA_CLK frequency⁽¹⁾	Depends on capacitive load on the I/O lines, TI recommends 2 MHz⁽¹⁾	2	4	10	MHz
R_OUT	Output resistance I/O_0 to I/O_7			500	800	Ω
R_{SYS_CLK}	Output resistance R_{SYS_CLK}			200	400	Ω

(1) Measured with subcarrier signal at RX_IN1 or RX_IN2 and measured the digital output at MOD pin with register 0x1A bit 6 = 1.

(2) Depends on the crystal parameters and components

(3) Antenna driver output resistance

5.5 Thermal Resistance Characteristics

PACKAGE	θ_JC	θ_JA⁽¹⁾	POWER RATING⁽²⁾
PACKAGE	θ_JC	θ_JA⁽¹⁾	T_A ≤ 25°C	T_A ≤ 85°C
RHB (32 pin)	31°C/W	36.4°C/W	2.7 W	1.1 W

(1) This data was taken using the JEDEC standard high-K test PCB.

(2) Power rating is determined with a junction temperature of 125°C. This is the temperature at which distortion starts to increase substantially. Thermal management of the final PCB should strive to keep the junction temperature at or below 125°C for best performance and long-term reliability.

5.6 Switching Characteristics

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_LO/HI	DATA_CLK time high or low, one half of DATA_CLK at 50% duty cycle	Depends on capacitive load on the I/O lines⁽¹⁾	250	62.5	50	ns
t_STE,LEAD	Slave select lead time, slave select low to clock			200		ns
t_STE,LAG	Slave select lag time, last clock to slave select high			200		ns
t_STE,DIS	Slave select disable time, slave select rising edge to next slave select falling edge		300			ns
t_SU,SI	MOSI input data setup time		15			ns
t_HD,SI	MOSI input data hold time		15			ns
t_SU,SO	MISO input data setup time		15			ns
t_HD,SO	MISO input data hold time		15			ns
t_VALID,SO	MISO output data valid time	DATA_CLK edge to MISO valid, C_L ≤ 30 pF	30	50	75	ns

(1) TI recommends a DATA_CLK speed of 2 MHz. Higher data clock depends on the capacitive load. Maximum SPI clock speed should not exceed 10 MHz. This clock speed is acceptable only when external capacitive load is less than 30 pF. MISO driver has a typical output resistance of 400 Ω (12-ns time constant when 30-pF load used).