ZHCSQF3B april 2022 – june 2023 TPSI2140-Q1
PRODUCTION DATA
When the voltage between the S1 and S2 pins exceeds +/-1200 V the secondary side MOSFETs could enter an avalanche mode of operation. The MOSFETs and the 11 DWQ package have been designed and qualified to be robust in this mode of operation to support Dielectric Withstand Testing (HiPot). To help ensure the thermal performance of the the system in this mode of operation, refer to the PCB Layout Guidelines.