ZHCSQF3B april 2022 – june 2023 TPSI2140-Q1
PRODUCTION DATA
- 1
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Parameter Measurement Information
- 8 Detailed Description
- 9 Application and Implementation
- 10Device and Documentation Support
- 11Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- DWQ|11
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
訂購信息
9.2.3 Design Procedure - Chassis Ground Reference
Figure 9-11 Chassis Ground Reference RISO1 Selection
In order to protect the TPSI2140-Q1, RISO1 must be sized to limit the current in an overvoltage condition. The amount of resistance required to protect the TPSI2140-Q1 depends on the amount of overvoltage applied. For example, during a dielectric withstand voltage test (HiPot) of 3500 V for 5 seconds, the S1 to S2 voltage will be clamped to 1300 V (VAVA minimum) by the TPSI2140-Q1 and the RISO1 resistance required to keep the current under 2 mA would be 1.1 MΩ.
If the high potential test lasts for 60 seconds, the RISO1 resistance must be doubled to 2.2 MΩ to keep the current below 1 mA.
DC Overvoltage | RISO1 Minimum (5 second intervals) | RISO1 Minimum (60 second intervals) |
|---|---|---|
|
2000 V |
350 kΩ |
700 kΩ |
|
2500 V |
600 kΩ |
1200 kΩ |
|
3500 V |
1100 kΩ |
2200 kΩ |
|
4300 V |
1500 kΩ |
3000 MΩ |