ZHCSIY0 October 2018 TPS92515AHV-Q1
PRODUCTION DATA.
| PARAMETER | TEST CONDITION | MIN | TYP | MAX | UNIT | |
| PEAK CURRENT COMPARATOR | ||||||
| VCST | VIN– VCSN peak current threshold | VIADJ = VCC | 222 | 240 | 257 | mV |
| VIADJ = 2.2 V | 205 | 220 | 234 | mV | ||
| AADJ | VIADJ to VIN – VCSN threshold gain | 0.1 ≤ VIADJ ≤ 2.2 V | 0.1 | V/V | ||
| tDEL | CSN pin falling delay | CSN fall to SW fall | 75 | 130 | ns | |
| tLEB | Minimum ON-time | Minimum pulse width | 75 | 195 | 275 | ns |
| SYSTEM CURRENTS | ||||||
| Icq | Operating current | Not switching, VIADJ = VVCC | 0.85 | 1.5 | mA | |
| INTEGRATED N-Channel MOSFET AND DRIVER | ||||||
| RDS(on) | FET ON-resistance | IDRN-SW = 200 mA, VBOOT = 5 V,
TJ = 25°C |
290 | 500 | mΩ | |
| IDRN-SW = 200 mA, VBOOT = 5 V,
TJ = 150°C |
290 | 600 | ||||
| IDRN-SW = 200 mA, VBOOT = 3.5 V,
TJ = 25°C |
310 | 500 | ||||
| IDRN-SW = 200 mA, VBOOT = 3.5 V,
TJ = 150°C |
310 | 650 | ||||
| IDRN-SW(off) | FET leakage current | VDRN-SW = 6 V, VSW = 0 V | 10 | µA | ||
| VBOOT-UVLO | Voltage where gate drive is disabled | VBOOT falling | 2.0 | 2.8 | 3.5 | V |
| VBOOT-UVLO(hys) | BOOT pin UVLO Hysteresis | 125 | mV | |||
| IPD(PWM/UVLO) | Pull down from SW when PWM low. | PWM low, VBOOT = 5 V , VSW = 8 V | 100 | 130 | µA | |
| IPD(BOOT) | Pull down from SW when VBOOT reaches VBOOT-UVLO | PWM high, VBOOT < BOOT-UVLO, VSW = 8 V | 5 | 7 | mA | |
| IBOOT_Q | BOOT pin quiescent current | VBOOT = 5.5 V, 0 V ≤ VSW ≤ 65 V | 60 | 90 | µA | |
| VCC/REFERENCE REGULATOR | ||||||
| VCC | Regulated pin voltage | IVCC(ext) ≤ 500 µA | 4.8 | 5.0 | 5.2 | V |
| VCCDO | Drop out voltage | IVCC(ext) ≤ 500 µA | 0.1 | 0.2 | V | |
| VCCUVLO | VCC undervoltage lockout | Falling threshold, VIN = 10 V | 4.0 | 4.2 | 4.4 | V |
| VCCUVLO_hys | VCC undervoltage lockout hysteresis | 0.22 | V | |||
| IVCC(ILIM) | VCC regulator current limit | VCC shorted to GND | 14 | 19 | 23 | mA |
| VINUVLO | VIN UVLO Falling Threshold | 4.65 | 4.90 | 5.15 | V | |
| VINUVLO_hys | VIN UVLO Hysteresis | 150 | 190 | 225 | mV | |
| OFF-TIMER | ||||||
| VOFT | OFF-time threshold | 0.95 | 1.00 | 1.05 | V | |
| tD(off) | COFF threshold | COFF to SW rising delay | 68 | 120 | ns | |
| tOFF(max) | Maximum OFF-time | 230 | µs | |||
| PWM/UVLO (Enable) | ||||||
| IPWM(uvlo) | PWM/UVLO pin current | VPWM(uvlo) = 5.5 V | 10 | nA | ||
| VPWM(uvlo) | PWM/UVLO pin threshold | PWM pin rising | 0.95 | 1.0 | 1.05 | V |
| VPWM(uvlo-hys) | PWM/UVLO pin hysteresis | Difference between rising and falling threshold | 50 | 100 | 150 | mV |
| tPWM(uvlo) | PWM/UVLO pin delay | PWM pin rising to SW pin rising | 75 | 130 | ns | |
| PWM pin falling to SW pin falling | 100 | 170 | ns | |||
| IPWM(uvlo-hys) | PWM/UVLO hysteresis current | VPWM(uvlo) = 2 V | –25 | –20 | –15 | μA |
| THERMAL SHUTDOWN | ||||||
| TSD | Thermal shutdown temperature | 175 | °C | |||
| TSD(hyst) | Thermal shutdown hysteresis | 10 | ||||