ZHCSL68C April 2017 – December 2020 TPS7A84A
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Electrical Characteristics: General
- 6.6 Electrical Characteristics: TPS7A8400A
- 6.7 Electrical Characteristics: TPS7A8401A
- 6.8 Typical Characteristics: TPS7A8400A
- 6.9 Typical Characteristics: TPS7A8401A
- 7 Detailed Description
-
8 Application and Implementation
- 8.1
Application Information
- 8.1.1
External Component Selection
- 8.1.1.1 Adjustable Operation
- 8.1.1.2 ANY-OUT Programmable Output Voltage
- 8.1.1.3 ANY-OUT Operation
- 8.1.1.4 Increasing ANY-OUT Resolution for LILO Conditions
- 8.1.1.5 Current Sharing
- 8.1.1.6 Recommended Capacitor Types
- 8.1.1.7 Input and Output Capacitor Requirements (CIN and COUT)
- 8.1.1.8 Feed-Forward Capacitor (CFF)
- 8.1.1.9 Noise-Reduction and Soft-Start Capacitor (CNR/SS)
- 8.1.2 Start-Up
- 8.1.3 AC and Transient Performance
- 8.1.4 DC Performance
- 8.1.5 Sequencing Requirements
- 8.1.6 Negatively Biased Output
- 8.1.7 Reverse Current Protection
- 8.1.8 Power Dissipation (PD)
- 8.1.1
External Component Selection
- 8.2 Typical Applications
- 8.1
Application Information
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
7.3.2.2 Internal Sequencing
Controlling when a single power supply turns on can be difficult in a power distribution network (PDN) because of the high power levels inherent in a PDN, and the variations between all of the supplies. The LDO turnon and turnoff time is set by the enable circuit (EN) and undervoltage lockout circuits (UVLO1,2(IN) and UVLOBIAS), as shown in Figure 7-5 and Table 7-2.
Figure 7-5 Simplified Turnon ControlTable 7-2 Internal Sequencing Functionality Table
| INPUT VOLTAGE | BIAS VOLTAGE | ENABLE STATUS | LDO STATUS | ACTIVE DISCHARGE | POWER GOOD |
|---|---|---|---|---|---|
| VIN ≥ VUVLO_1,2(IN) | VBIAS ≥ VUVLO(BIAS) | EN = 1 | On | Off | PG = 1 when VOUT ≥ VIT(PG) |
| EN = 0 | Off | On | PG = 0 | ||
| VBIAS < VUVLO(BIAS) +VHYS(BIAS) | EN = don't care | Off | On (1) | ||
| VIN < VUVLO_1,2(IN) – VHYS1,2(IN) | BIAS = don't care | Off | |||
| IN = don't care | VBIAS ≥ VUVLO(BIAS) | Off |
(1) The active discharge remains on as long as VIN or VBIAS provides enough headroom for the discharge circuit to function.