ZHCSFL8C October 2016 – August 2021 TPS65983B
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 說明（續(xù)）
- 6 Pin Configuration and Functions
-
7 Specifications
- 7.1 Absolute Maximum Ratings
- 7.2 ESD Ratings
- 7.3 Recommended Operating Conditions
- 7.4 Thermal Information
- 7.5 Power Supply Requirements and Characteristics
- 7.6 Power Supervisor Characteristics
- 7.7 Power Consumption Characteristics
- 7.8 Cable Detection Characteristics
- 7.9 USB-PD Baseband Signal Requirements and Characteristics
- 7.10 USB-PD TX Driver Voltage Adjustment Parameter (1)
- 7.11 Port Power Switch Characteristics
- 7.12 Port Data Multiplexer Switching and Timing Characteristics
- 7.13 Port Data Multiplexer Clamp Characteristics
- 7.14 Port Data Multiplexer SBU Detection Requirements
- 7.15 Port Data Multiplexer Signal Monitoring Pullup and Pulldown Characteristics
- 7.16 Port Data Multiplexer USB Endpoint Requirements and Characteristics
- 7.17 Port Data Multiplexer BC1.2 Detection Requirements and Characteristics
- 7.18 Analog-to-Digital Converter (ADC) Characteristics
- 7.19 Input/Output (I/O) Requirements and Characteristics
- 7.20 I2C Slave Requirements and Characteristics
- 7.21 SPI Controller Characteristics
- 7.22 Single-Wire Debugger (SWD) Timing Requirements
- 7.23 BUSPOWERZ Configuration Requirements
- 7.24 HPD Timing Requirements and Characteristics
- 7.25 Thermal Shutdown Characteristics
- 7.26 Oscillator Requirements and Characteristics
- 7.27 Typical Characteristics
- 8 Parameter Measurement Information
-
9 Detailed Description
- 9.1 Overview
- 9.2 Functional Block Diagram
- 9.3
Feature Description
- 9.3.1 USB-PD Physical Layer
- 9.3.2 Cable Plug and Orientation Detection
- 9.3.3
Port Power Switches
- 9.3.3.1 5V Power Delivery
- 9.3.3.2 5V Power Switch as a Source
- 9.3.3.3 PP_5V0 Current Sense
- 9.3.3.4 PP_5V0 Current Limit
- 9.3.3.5 Internal HV Power Delivery
- 9.3.3.6 Internal HV Power Switch as a Source
- 9.3.3.7 Internal HV Power Switch as a Sink
- 9.3.3.8 Internal HV Power Switch Current Sense
- 9.3.3.9 Internal HV Power Switch Current Limit
- 9.3.3.10 External HV Power Delivery
- 9.3.3.11 External HV Power Switch as a Source with RSENSE
- 9.3.3.12 External HV Power Switch as a Sink with RSENSE
- 9.3.3.13 External HV Power Switch as a Sink without RSENSE
- 9.3.3.14 External Current Sense
- 9.3.3.15 External Current Limit
- 9.3.3.16 Soft Start
- 9.3.3.17 BUSPOWERZ
- 9.3.3.18 Voltage Transitions on VBUS through Port Power Switches
- 9.3.3.19 HV Transition to PP_RV0 Pull-Down on VBUS
- 9.3.3.20 VBUS Transition to VSAVE0V
- 9.3.3.21 C_CC1 and C_CC2 Power Configuration and Power Delivery
- 9.3.3.22 PP_CABLE to C_CC1 and C_CC2 Switch Architecture
- 9.3.3.23 PP_CABLE to C_CC1 and C_CC2 Current Limit
- 9.3.4
USB Type-C Port Data Multiplexer
- 9.3.4.1 USB Top and Bottom Ports
- 9.3.4.2 Multiplexer Connection Orientation
- 9.3.4.3 Digital Crossbar Multiplexer
- 9.3.4.4 SBU Crossbar Multiplexer
- 9.3.4.5 Signal Monitoring and Pullup and Pulldown
- 9.3.4.6 Port Multiplexer Clamp
- 9.3.4.7 USB2.0 Low-Speed Endpoint
- 9.3.4.8 Battery Charger (BC1.2) Detection Block
- 9.3.4.9 BC1.2 Data Contact Detect
- 9.3.4.10 BC1.2 Primary and Secondary Detection
- 9.3.5 Power Management
- 9.3.6 Digital Core
- 9.3.7 USB-PD BMC Modem Interface
- 9.3.8 System Glue Logic
- 9.3.9 Power Reset Congrol Module (PRCM)
- 9.3.10 Interrupt Monitor
- 9.3.11 ADC Sense
- 9.3.12 UART
- 9.3.13 I2C Slave
- 9.3.14 SPI Controller
- 9.3.15 Single-Wire Debugger Interface
- 9.3.16 DisplayPort HPD Timers
- 9.3.17 ADC
- 9.3.18 I/O Buffers
- 9.3.19 Thermal Shutdown
- 9.3.20 Oscillators
- 9.4 Device Functional Modes
- 9.5 Programming
-
10Application and Implementation
- 10.1 Application Information
- 10.2
Typical Application
- 10.2.1
Fully-Featured USB Type-C and PD Charger Application
- 10.2.1.1 Design Requirements
- 10.2.1.2
Detailed Design Procedure
- 10.2.1.2.1 TPS65983B External Flash
- 10.2.1.2.2 I2C (I2C), Debug Control (DEBUG_CTL), and Single-Wire De-bugger (SWD) Resistors
- 10.2.1.2.3 Oscillator (R_OSC) Resistor
- 10.2.1.2.4 VBUS Capacitor and Ferrite Bead
- 10.2.1.2.5 Soft Start (SS) Capacitor
- 10.2.1.2.6 USB Top (C_USB_T), USB Bottom (C_USB_B), and Sideband-Use (SBU) Connections
- 10.2.1.2.7 Port Power Switch (PP_EXT, PP_HV, PP_5V0, and PP_CABLE) Capacitors
- 10.2.1.2.8 Cable Connection (CCn) Capacitors and RPD_Gn Connections
- 10.2.1.2.9 LDO_3V3, LDO_1V8A, LDO_1V8D, LDO_BMC, VOUT_3V3, VIN_3V3, and VDDIO
- 10.2.1.3 Application Curve
- 10.2.2 Dual-Port Notebook Application Supporting USB PD Charging and DisplayPort
- 10.2.1
Fully-Featured USB Type-C and PD Charger Application
- 11Power Supply Recommendations
-
12Layout
- 12.1
Layout Guidelines
- 12.1.1 TPS65983B Recommended Footprints
- 12.1.2 Alternate TPS65983B Footprint (Oval Pads)
- 12.1.3 Top TPS65983B Placement and Bottom Component Placement and Layout
- 12.1.4 Oval Pad Footprint Layout and Placement
- 12.1.5 Component Placement
- 12.1.6 Designs Rules and Guidance
- 12.1.7 Routing PP_HV, PP_EXT, PP_5V0, and VBUS
- 12.1.8 Routing Top and Bottom Passive Components
- 12.1.9 Void Via Placement
- 12.1.10 Top Layer Routing
- 12.1.11 Inner Signal Layer Routing
- 12.1.12 Bottom Layer Routing
- 12.2 Layout Example
- 12.1
Layout Guidelines
- 13Device and Documentation Support
- 14Mechanical, Packaging, and Orderable Information
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
- ZBH|96
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
訂購信息
6 Pin Configuration and Functions
Figure 6-1 ZQZ and ZBH Package 96-Pin BGA MicroStar Junior and NFBGATop View
Figure 6-2 Legend for Pinout DrawingTable 6-1 Pin Functions
| PIN | TYPE | POR STATE |
DESCRIPTION | |
|---|---|---|---|---|
| NAME | NO. | |||
| HIGH-CURRENT POWER PINS | ||||
| PP_5V0 | A11, B11, C11, D11 | Power | NA | 5-V supply for VBUS. Bypass with capacitance CPP_5V0 to GND. Tie pin to GND when unused |
| PP_HV | A6, A7, A8, B7 | Power | NA | HV supply for VBUS. Bypass with capacitance CPP_HV to GND. Tie pin to GND when unused |
| PP_CABLE | H10 | Power | NA | 5-V supply for C_CC pins. Bypass with capacitance CPP_CABLE to GND when not tied to PP_5V0. Tie pin to PP_5V0 when unused. |
| VBUS | H11, J10, J11, K11 | Power | NA | 5-V output from PP_5V0. Input or output from PP_HV up to 20 V. Bypass with capacitance CVBUS to GND. |
| LOW-CURRENT POWER PINS | ||||
| VIN_3V3 | H1 | Power | NA | Supply for core circuitry and I/O. Bypass with capacitance CVIN_3V3 to GND. |
| VDDIO | B1 | Power | NA | VDD for I/O. Some I/Os are reconfigurable to be powered from VDDIO instead of LDO_3V3. When VDDIO is not used, tie pin to LDO_3V3. When not tied to LDO_3V3 and used as a supply input, bypass with capacitance CVDDIO to GND. |
| VOUT_3V3 | H2 | Power | NA | Output of supply switched from VIN_3V3. Bypass with capacitance COUT_3V3 to GND. Float pin when unused. |
| LDO_3V3 | G1 | Power | NA | Output of the VBUS to 3.3 V LDO or connected to VIN_3V3 by a switch. Main internal supply rail. Used to power external flash memory. Bypass with capacitance CLDO_3V3 to GND. |
| LDO_1V8A | K1 | Power | NA | Output of the 3.3 V or 1.8 V LDO for Core Analog Circuits. Bypass with capacitance CLDO_1V8A to GND. |
| LDO_1V8D | A2 | Power | NA | Output of the 3.3 V or 1.8 V LDO for Core Digital Circuits. Bypass with capacitance CLDO_1V8D to GND. |
| LDO_BMC | E1 | Power | NA | Output of the USB-PD BMC transceiver output level LDO. Bypass with capacitance CLDO_BMC to GND. |
| TYPE-C PORT PINS | ||||
| C_CC1 | L9 | Analog I/O | Hi-Z | Output to Type-C CC or VCONN pin. Filter noise with capacitance CC_CC1 to GND. |
| C_CC2 | L10 | Analog I/O | Hi-Z | Output to Type-C CC or VCONN pin. Filter noise with capacitance CC_CC2 to GND. |
| RPD_G1 | K9 | Analog I/O | Hi-Z | Tie pin to C_CC1 when configured to receive power in dead-battery or no-power condition. Tie pin to GND otherwise. |
| RPD_G2 | K10 | Analog I/O | Hi-Z | Tie pin to C_CC2 when configured to receive power in dead-battery or no-power condition. Tie pin to GND otherwise. |
| C_USB_TP | K6 | Analog I/O | Hi-Z | Port side Top USB D+ connection to Port Multiplexer. |
| C_USB_TN | L6 | Analog I/O | Hi-Z | Port side Top USB D– connection to Port Multiplexer. |
| C_USB_BP | K7 | Analog I/O | Hi-Z | Port side Bottom USB D+ connection to Port Multiplexer. |
| C_USB_BN | L7 | Analog I/O | Hi-Z | Port side Bottom USB D– connection to Port Multiplexer. |
| C_SBU1 | K8 | Analog I/O | Hi-Z | Port side Sideband Use connection of Port Multiplexer. |
| C_SBU2 | L8 | Analog I/O | Hi-Z | Port side Sideband Use connection of Port Multiplexer. |
| PORT MULTIPLEXER PINS | ||||
| SWD_DATA | F4 | Digital I/O | Resistive Pull High | SWD serial data. Float pin when unused. |
| SWD_CLK | G4 | Digital Input | Resistive Pull High | SWD serial clock. Float pin when unused. |
| UART_RX | F2 | Digital Input | Digital Input | UART serial receive data. Connect pin to another TPS65983B UART_TX to share firmware. Connect UART_RX to UART_TX when not connected to another TPS65983B and ground pin through a 100 kΩ resistance. |
| UART_TX | E2 | Digital Output | UART_RX | UART serial transmit data. Connect pin to another TPS65983B UART_TX to share firmware. Connect UART_RX to UART_TX when not connected to another TPS65983B. |
| USB_RP_P | L5 | Analog I/O | Hi-Z | System side USB2.0 high-speed connection to Port Multiplexer. Ground pin with between 1-kΩ and 5-MΩ resistance when unused. |
| USB_RP_N | K5 | Analog I/O | Hi-Z | System side USB2.0 high-speed connection to Port Multiplexer. Ground pin with between 1-kΩ and 5-MΩ resistance when unused. |
| LSX_R2P | L4 | Digital Input | Digital Input | System side low speed TX from system to port. This pin is configurable to be an input to the digital core or the crossbar multiplexer to the port. Ground pin with between 1-kΩ and 5-MΩ resistance when unused. |
| LSX_P2R | K4 | Digital Output | Hi-Z | System side low speed RX to system from port. This pin is configurable to be an output from the digital core or the crossbar multiplexer from the port. Float pin when unused. |
| AUX_P | J1 | Analog I/O | Hi-Z | System side DisplayPort connection to Port Multiplexer. Ground pin with between 1-kΩ and 5-MΩ resistance when unused. |
| AUX_N | J2 | Analog I/O | Hi-Z | System side DisplayPort connection to Port Multiplexer. Ground pin with between 1-kΩ and 5-MΩ resistance when unused. |
| EXTERNAL HV FET CONTROL/SENSE PINS AND SOFT START | ||||
| SENSEP | B10 | Analog Input | Analog Input | Positive sense for external high voltage power path current sense resistance. Short pin to VBUS when unused. |
| SENSEN | A10 | Analog Input | Analog Input | Positive sense for external high voltage power path current sense resistance. Short pin to VBUS when unused. |
| HV_GATE1 | B9 | Analog Output | Short to SENSEP | External NFET gate control for high voltage power path. Float pin when unused. |
| HV_GATE2 | A9 | Analog Output | Short to VBUS | External NFET gate control for high voltage power path. Float pin when unused. |
| SS | H7 | Analog Output | Driven Low | Soft Start. Tie pin to capacitance CSS to ground. |
| DIGITAL CORE I/O AND CONTROL PINS | ||||
| R_OSC | G2 | Analog I/O | Hi-Z | External resistance setting for oscillator accuracy. Connect R_OSC to GND through resistance RR_OSC. |
| GPIO0 (HD3 AMSEL) |
B2 | Digital I/O | Hi-Z | General Purpose Digital I/O 0. Alternate mode select signal to external Super Speed multiplexer (tri-state capable with pullup and pulldown resistors). Ground pin with a 1-MΩ resistor when unused in the application. |
| GPIO1 (CONFIG0) |
C2 | Digital I/O | Hi-Z | General Purpose Digital I/O 1. Must be tied high or low through a 1 kΩ pullup or pulldown resistor when used as a configuration input. |
| GPIO2 | D10 | Digital I/O | Hi-Z | General Purpose Digital I/O 2. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application. |
| GPIO3 (HD3 EN) |
G11 | Digital I/O | Hi-Z | General Purpose Digital I/O 3. Enable signal to external Super Speed multiplexer. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application. |
| GPIO4 (HPD TXRX) |
C10 | Digital I/O | Hi-Z | General Purpose Digital I/O 4. Configured as Hot Plug Detect (HPD) TX and/or HPD RX when DisplayPort Mode supported. Ground pin with a 1-MΩ resistor when unused in the application. |
| GPIO5 (HPD RX) |
E10 | Digital I/O | Hi-Z | General Purpose Digital I/O 5. Can be configured as Hot Plug Detect (HPD) RX when DisplayPort Mode supported. Must be tied high or low through a 1 kΩ pullup or pulldown resistor when used as a configuration input. Ground pin with a 1-MΩ resistor when unused in the application. |
| GPIO6 | G10 | Digital I/O | Hi-Z | General Purpose Digital I/O 6. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application. |
| GPIO7 | D7 | Digital I/O | Hi-Z | General Purpose Digital I/O 7. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application. |
| GPIO8 | H6 | Digital I/O | Hi-Z | General Purpose Digital I/O 8. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application. |
| RESETZ (GPIO9) |
F11 | Digital I/O | Push-Pull Output (Low) | General Purpose Digital I/O 9. Active low reset output when VOUT_3V3 is low (driven low on start-up). Float pin when unused. |
| BUSPOWERZ (GPIO10) |
F10 | Analog Input | Input (Hi-Z) | General Purpose Digital I/O 10. Sampled by ADC at boot. Tie pin to LDO_3V3 through a 100-kΩ resistor to disable PP_HV and PP_EXT power paths during dead-battery or no-battery boot conditions. Refer to the Section 9.3.3.17 table for more details. |
| MRESET (GPIO11) |
E11 | Digital I/O | Hi-Z | General Purpose Digital I/O 11. Forces RESETZ to assert. By default, this pin asserts RESETZ when pulled high. The pin can be programmed to assert RESETZ when pulled low. Ground pin with a 1-MΩ resistor when unused in the application. |
| DEBUG4 (GPIO12, CONFIG2) |
K3 | Digital I/O | Hi-Z | General Purpose Digital I/O 12. Must be tied high or low through a 1-kΩ pullup or pulldown resistor when used as a configuration input. |
| DEBUG3 (GPIO13, CONFIG1) |
L3 | Digital I/O | Hi-Z | General Purpose Digital I/O 13. Must be tied high or low through a 1-kΩ pullup or pulldown resistor when used as a configuration input. |
| DEBUG2 (GPIO14, HD3 POL) |
K2 | Digital I/O | Hi-Z | General Purpose Digital I/O 14. Polarity signal to external Super Speed multiplexer. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application. |
| DEBUG1 (GPIO15) |
L2 | Digital I/O | Hi-Z | General Purpose Digital I/O 15. Ground pin with a 1-MΩ resistor when unused in the application. |
| DEBUG_CTL1 (GPIO16, I2C ADDR B4) |
E4 | Digital I/O | Hi-Z | General Purpose Digital I/O 16. At power-up, pin state is sensed to determine bit 4 of the I2C address. |
| DEBUG_CTL2 (GPIO17, I2C ADDR B5) |
D5 | Digital I/O | Hi-Z | General Purpose Digital I/O 17. At power-up, pin state is sensed to determine bit 5 of the I2C address. |
| HRESET | D6 | Digital Input | Hi-Z | Active high hardware reset input. Will re-load settings from external flash memory. Ground pin when HRESET functionality will not be used. |
| I2C_SDA1 | D1 | Digital I/O | Digital Input | I2C port 1 serial data. Open-drain output. Tie pin to LDO_3V3 or VDDIO (depending on configuration) through a 10-kΩ resistor when used or unused. |
| I2C_SCL1 | D2 | Digital I/O | Digital Input | I2C port 1 serial clock. Open-drain output. Tie pin to LDO_3V3 or VDDIO (depending on configuration) through a 10-kΩ resistor when used or unused. |
| I2C_IRQ1Z | C1 | Digital Output | Hi-Z | I2C port 1 interrupt. Active low. Implement externally as an open drain with a pullup resistance. Float pin when unused. |
| I2C_SDA2 | A5 | Digital I/O | Digital Input | I2C port 2 serial data. Open-drain output. Tie pin to LDO_3V3 or VDDIO (depending on configuration) through a 10-kΩ resistor when used or unused. |
| I2C_SCL2 | B5 | Digital I/O | Digital Input | I2C port 2 serial clock. Open-drain output. Tie pin to LDO_3V3 or VDDIO (depending on configuration) through a 10-kΩ resistor when used or unused. |
| I2C_IRQ2Z | B6 | Digital Output | Hi-Z | I2C port 2 interrupt. Active low. Implement externally as an open drain with a pullup resistance. Float pin when unused. |
| I2C_ADDR | F1 | Analog I/O | Analog Input | Sets the I2C address for both I2C ports as well as determine the controller and slave devices for memory code sharing. |
| SPI_CLK | A3 | Digital Output | Digital Input | SPI serial clock. Ground pin when unused |
| SPI_PICO | B4 | Digital Output | Digital Input | SPI serial controller output to peripheral. Ground pin when unused. |
| SPI_POCI | A4 | Digital Input | Digital Input | SPI serial controller input from peripheral. This pin is used during boot sequence to determine if the flash memory is valid. Refer to the Boot Code section for more details. Ground pin when unused. |
| SPI_CSZ | B3 | Digital Output | Digital Input | SPI chip select. Ground pin when unused. |
| GROUND AND NO CONNECT PINS | ||||
| GND | A1, B8, D8, E5, E6, E7, E8, F5, F6, F7, F8, G5, G6, G7, G8, H4, H5, H8, L1 | Ground | NA | Ground. Connect all balls to ground plane. |
| NC | L11 | Blank | NA | Populated Ball that must remain unconnected. |
| No Ball | C3, C4, C5, C6, C7, C8, C9, D3, D4, D9, E3, E9, F3, F9, G3, G9, H3, H9, J3, J4, J5, J6, J7, J8, J9 | Blank | NA | Unpopulated ball for A1 marker and unpopulated inner ring. |