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ZHCSI09S June 2010 – August 2018 TPS65911

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

ZRC|98
- MPBG381
NMA|98
- MPBGAT4A

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

5.21.1 I²C Timing and Switching

In Table 5-1, SDA is the SDA_SDI or EN2 signal and SCL is the SCL_SCK or EN1 signal. The input timing requirements are given by considering a rising or falling time of 80 ns in high–speed mode (3.4 Mbps), 300 ns in fast–speed mode (400 kbps), 1000 ns in standard mode (100 kbps). Values are over the operating free-air temperature range unless otherwise noted.

Table 5-1 Timing Requirements: I²C Interface and Control Signals

NO.				MIN	NOM	UNIT
		INT1 rise and fall times	C_L = 5 to 35 pF	5	10	ns
		NRESPWRON rise and fall times	C_L = 5 to 35 pF	5	10	ns
SLAVE HIGH–SPEED MODE
		SCL/EN1 and SDA/EN2 rise and fall time	C_L = 10 to 100 pF	10	80	ns
		Data rate			3.4	Mbps
I3	t_su(SDA-SCLH)	Setup time, SDA valid to SCL high		10		ns
I4	t_h(SCLL-SDA)	Hold time, SDA valid from SCL low		0	70	ns
I7	t_{su(SCLH-SDAL)}	Setup time, SCL high to SDA low		160		ns
I8	t_h(SDAL-SCLL)	Hold time, SCL low from SDA low		160		ns
I9	t_{su(SDAH-SCLH)}	Setup time, SDA high to SCL high		160		ns
SLAVE FAST MODE
		SCL/EN1 and SDA/EN2 rise and fall time	C_L = 10 to 400 pF	20 + 0.1 × C_L	250	ns
		Data rate			400	Kbps
I3	t_su(SDA-SCLH)	Setup time, SDA valid to SCL high		100		ns
I4	t_h(SCLL-SDA)	Hold time, SDA valid from SCL low		0	0.9	µs
I7	t_{su(SCLH-SDAL)}	Setup time, SCL high to SDA low		0.6		µs
I8	t_h(SDAL-SCLL)	Hold time, SCL low from SDA low		0.6		µs
I9	t_{su(SDAH-SCLH)}	Setup time, SDA high to SCL high		0.6		µs
SLAVE STANDARD MODE
		SCL/EN1 and SDA/EN2 rise and fall time	C_L = 10 to 400 pF		250	ns
		Data rate			100	Kbps
I3	t_su(SDA-SCLH)	Setup time, SDA valid to SCL high		250		ns
I4	t_h(SCLL-SDA)	Hold time, SDA valid from SCL low		0		µs
I7	t_{su(SCLH-SDAL)}	Setup time, SCL high to SDA low		4.7		µs
I8	t_h(SDAL-SCLL)	Hold time, SCL low from SDA low		4		µs
I9	t_{su(SDAH-SCLH)}	Setup time, SDA high to SCL high		4		µs

In Table 5-2, SCL is the SCL_SCK or EN1 signal. The input timing requirements are given by considering a rising or falling time of 80 ns in high–speed mode (3.4 Mbps), 300 ns in fast–speed mode (400 kbps), 1000 ns in standard mode (100 kbps). Values are over the operating free-air temperature range unless otherwise noted.

Table 5-2 Switching Characteristics: I²C Interface and Control Signals

NO.	PARAMETER		MIN	UNIT
SLAVE HIGH–SPEED MODE
I1	t_w(SCLL)	Pulse duration, SCL low	160	ns
I2	t_w(SCLH)	Pulse duration, SCL high	60	ns
SLAVE FAST MODE
I1	t_w(SCLL)	Pulse duration, SCL low	1.3	µs
I2	t_w(SCLH)	Pulse duration, SCL high	0.6	µs
SLAVE STANDARD MODE
I1	t_w(SCLL)	Pulse duration, SCL low	4.7	µs
I2	t_w(SCLH)	Pulse duration, SCL high	4	µs