ZHCSHO2G June 2010 – February 2018 TPS65251
PRODUCTION DATA.
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| INPUT SUPPLY UVLO AND INTERNAL SUPPLY VOLTAGE | ||||||
| VIN | Input Voltage range | 4.5 | 18 | V | ||
| IDDSDN | Shutdown | EN pin = low for all converters | 1.3 | mA | ||
| IDDQ | Quiescent, low-power disabled (Lo) | Converters enabled, no load
Buck 1 = 3.3 V, Buck 2 = 2.5 V, Buck 3 = 7.5 V, L = 4.7 µH , fSW = 800 kHz |
20 | mA | ||
| IDDQ_LOW_P | Quiescent, low-power enabled (Hi) | Converters enabled, no load
Buck 1 = 3.3 V, Buck 2 = 2.5 V, Buck 3 = 7.5 V, L = 4.7 µH , fSW = 800 kHz |
1.5 | mA | ||
| UVLOVIN | VIN under voltage lockout | Rising VIN | 4.22 | V | ||
| Falling VIN | 4.1 | |||||
| UVLODEGLITCH | Both edges | 110 | µs | |||
| V3V | Internal biasing supply | ILOAD = 0 mA | 3.2 | 3.3 | 3.4 | V |
| I3V | Biasing supply output current | VIN = 12 V | 10 | mA | ||
| V7V | Internal biasing supply | ILOAD = 0 mA | 5.63 | 6.25 | 6.88 | V |
| I7V | Biasing supply output current | VIN = 12 V | 10 | mA | ||
| V7VUVLO | UVLO for internal V7V rail | Rising V7V | 3.8 | V | ||
| Falling V7V | 3.6 | |||||
| V7VUVLO_DEGLITCH | Falling edge | 110 | µs | |||
| BUCK CONVERTERS (ENABLE CIRCUIT, CURRENT LIMIT, SOFT-START, SWITCHING FREQUENCY AND SYNC CIRCUIT, LOW-POWER MODE) | ||||||
| VIH | Enable threshold high | V3p3 = 3.2 V - 3.4 V, VENX rising | 1.55 | 1.82 | V | |
| Enable high level | External GPIO, VENX rising | 0.66 x V3V | ||||
| VIL | Enable threshold low | V3p3 = 3.2 V - 3.4 V, VENX falling | 0.98 | 1.24 | V | |
| Enable low level | External GPIO, VENX falling | 0.33 x V3V | ||||
| REN_DIS | Enable discharge resistor | –10% | 2.1 | 10% | kΩ | |
| ICHEN | Pullup current enable pin | 1.1 | µA | |||
| tD | Discharge time enable pins | Power-up | 10 | ms | ||
| ISS | Soft-start pin current source | 5 | µA | |||
| FSW_BK | Converter switching frequency range | Set externally with resistor | 0.3 | 2.2 | MHz | |
| RFSW | Frequency setting resistor | Depending on set frequency | 50 | 600 | kΩ | |
| fSW_TOL | Internal oscillator accuracy | fSW = 800 kHz | –10% | 10% | ||
| VSYNCH | External clock threshold high | V3p3 = 3.3 V | 1.55 | V | ||
| VSYNCL | External clock threshold Low | V3p3 = 3.3 V | 1.24 | V | ||
| SYNCRANGE | Synchronization range | 0.2 | 2.2 | MHz | ||
| SYNCCLK_MIN | Sync signal minimum duty cycle | 40% | ||||
| SYNCCLK_MAX | Sync signal maximum duty cycle | 60% | ||||
| VIHLOW_P | Low-power mode threshold high | V3p3 = 3.3 V, VENX rising | 1.55 | V | ||
| VILLOW_P | Low-power mode threshold Low | V3p3 = 3.3 V, VENX falling | 0.98 | 1.24 | V | |
| FEEDBACK, REGULATION, OUTPUT STAGE | ||||||
| VFB | Feedback voltage | VIN = 12V TJ = 25°C | –1% | 0.8 | 1% | V |
| VIN = 4.5 to 18 V | –2% | 0.8 | 2% | |||
| IFB | Feedback leakage current | 50 | nA | |||
| tON_MIN | Minimum on-time
(current sense blanking) |
80 | 120 | ns | ||
| VLINEREG | Line regulation - DC
?VOUT/?VINB |
VINB = 4.5 to 18 V,
IOUT = 1000 mA |
0.5 | % VOUT | ||
| VLOADREG | Load regulation - DC
?VOUT/?IOUT |
IOUT = 10 % - 90%
IOUT,MAX |
0.5 | % VOUT/A | ||
| MOSFET (BUCK 1) | ||||||
| H.S. Switch | Turn-On resistance high-side FET on CH1 | VIN = 12 V, TJ = 25°C | 95 | mΩ | ||
| L.S. Switch | Turn-On resistance low-side FET on CH1 | VIN = 12 V, TJ = 25°C | 50 | mΩ | ||
| MOSFET (BUCK 2) | ||||||
| H.S. Switch | Turn-On resistance high-side FET on CH2 | VIN = 12 V, TJ = 25°C | 120 | mΩ | ||
| L.S. Switch | Turn-On resistance low-side FET on CH2 | VIN = 12 V, TJ = 25°C | 80 | mΩ | ||
| MOSFET (BUCK 3) | ||||||
| H.S. Switch | Turn-On resistance high-side FET on CH3 | VIN = 12 V, TJ = 25°C | 120 | mΩ | ||
| L.S. Switch | Turn-On resistance low-side FET on CH3 | VIN = 12 V, TJ = 25°C | 80 | mΩ | ||
| ERROR AMPLIFIER | ||||||
| gM | Error amplifier transconductance | –2 µA < ICOMP< 2 µA | 130 | µS | ||
| gmPS | COMP to ILX gM | ILX = 0.5 A | 10 | A/V | ||
| POWERGOOD RESET GENERATOR | ||||||
| VUVBUCKX | Threshold voltage for buck under voltage | Output falling (device will be disabled after tON_HICCUP ) | 85% | |||
| Output rising (PG will be asserted) | 90% | |||||
| tUV_deglitch | Deglitch time (both edges) | Each buck | 11 | ms | ||
| tON_HICCUP | Hiccup mode ON time | VUVBUCKX asserted | 12 | ms | ||
| tOFF_HICCUP | Hiccup mode OFF time before restart is attempted | All converters disabled. Once tOFF_HICCUP elapses, all converters will go through sequencing again. | 15 | ms | ||
| VOVBUCKX | Threshold voltage for buck overvoltage | Output rising (high-side FET will be forced off) | 109% | |||
| Output falling (high-side FET will be allowed to switch ) | 107% | |||||
| tRP | Minimum reset period | Measured after minimum reset period of all bucks power-up successfully | 1 | s | ||
| THERMAL SHUTDOWN | ||||||
| TTRIP | Thermal shutdown trip point | Rising temperature | 160 | °C | ||
| THYST | Thermal shutdown hysteresis | Device restarts | 20 | °C | ||
| TTRIP_DEGLITCH | Thermal shutdown deglitch | 110 | µs | |||
| CURRENT LIMIT PROTECTION | ||||||
| RLIM1 | Limit resistance range Buck 1 | 75 | 300 | kΩ | ||
| RLIM2&3 | Limit resistance range Bucks 2 and 3 | 100 | 300 | kΩ | ||
| ILIM1 | Buck 1 adjustable current limit range | VIN = 12 V, fSW = 500 kHz,
see Figure 17 |
1.2 | 5.5 | A | |
| ILIM2 | Buck 2 adjustable current limit range | VIN = 12 V, fSW = 500 kHz,
see Figure 18 |
1 | 4.1 | A | |
| ILIM3 | Buck 3 adjustable current limit range | VIN = 12 V, fSW = 500 kHz,
see Figure 19 |
1.3 | 4.4 | A | |