ZHCSG04F january 2017 – may 2023 TPS65235-1
PRODUCTION DATA
- 1
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Boost Converter
- 7.3.2 Linear Regulator and Current Limit
- 7.3.3 Boost Converter Current Limit
- 7.3.4 Charge Pump
- 7.3.5 Slew Rate Control
- 7.3.6 Short-Circuit Protection, Hiccup, and Overtemperature Protection
- 7.3.7 Tone Generation
- 7.3.8 Tone Detection
- 7.3.9 Audio Noise Rejection
- 7.3.10 Disable and Enable
- 7.3.11 Component Selection
- 7.4 Device Functional Modes
- 7.5 Programming
- 7.6 Register Maps
- 8 Application and Implementation
- 9 Device and Documentation Support
- 10Mechanical, Packaging, and Orderable Information
8.2.1 DiSEqc1.x Support
TPS65235-1 can operate in I2C and non-I2C interface mode. Figure 8-1 shows the application with the device in I2C interface mode to support DiSEqC 1.x application. In non-I2C mode, the SCL, SDA, and ADDR pins can be floating.
Figure 8-1 Application for DiSEqc1.x Support