ZHCSE52B September 2015 – May 2019 TPS57140-EP
PRODUCTION DATA.
- 1 特性
- 2 應用范圍
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Fixed Frequency PWM Control
- 7.3.2 Slope-Compensation Output Current
- 7.3.3 Bootstrap Voltage (Boot)
- 7.3.4 Low-Dropout Operation
- 7.3.5 Error Amplifier
- 7.3.6 Voltage Reference
- 7.3.7 Adjusting the Output Voltage
- 7.3.8 Enable and Adjusting UVLO
- 7.3.9 Slow-Start or Tracking Pin (SS/TR)
- 7.3.10 Overload Recovery Circuit
- 7.3.11 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
- 7.3.12 Overcurrent Protection and Frequency Shift
- 7.3.13 Selecting the Switching Frequency
- 7.3.14 How to Interface to RT/CLK Pin
- 7.3.15 Power Good (PWRGD Pin)
- 7.3.16 Overvoltage Transient Protection (OVTP)
- 7.3.17 Thermal Shutdown
- 7.3.18 Small-Signal Model for Loop Response
- 7.3.19 Simple Small-Signal Model for Peak-Current-Mode Control
- 7.3.20 Small-Signal Model for Frequency Compensation
- 7.4 Device Functional Modes
-
8 Application and Implementation
- 8.1 Application Information
- 8.2
Typical Application
- 8.2.1 Design Requirements
- 8.2.2
Detailed Design Procedure
- 8.2.2.1 Selecting the Switching Frequency
- 8.2.2.2 Output Inductor Selection (LO)
- 8.2.2.3 Output Capacitor
- 8.2.2.4 Catch Diode
- 8.2.2.5 Input Capacitor
- 8.2.2.6 Slow-Start Capacitor
- 8.2.2.7 Bootstrap Capacitor Selection
- 8.2.2.8 UVLO Set Point
- 8.2.2.9 Output Voltage and Feedback Resistors Selection
- 8.2.2.10 Compensation
- 8.2.3 Application Curves
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
5 Pin Configuration and Functions
DRC Package
10-Pin VSON
Top View
Pin Functions
| PIN | I/O | DESCRIPTION | ||
|---|---|---|---|---|
| NAME | NO. | |||
| BOOT | 1 | O | The device requires a bootstrap capacitor between BOOT and PH. A voltage on this capacitor below the minimum required by the output device forces the output to switch off pending a refresh of the capacitor. | |
| COMP | 8 | O | Error-amplifier output and input to the output-switch current comparator. Connect frequency-compensation components to this pin. | |
| EN | 3 | I | Enable pin, internal pullup current source. Pull below 1.2 V to disable. Float to enable. Adjust the input UVLO with two resistors. | |
| GND | 9 | — | Ground | |
| PH | 10 | I | The source of the internal high-side power MOSFET | |
| PWRGD | 6 | O | An open-drain output, asserts low if output voltage is low due to thermal shutdown, dropout, overvoltage, or EN shutdown. | |
| RT/CLK | 5 | I | Resistor timing and external clock. An internal amplifier holds this pin at a fixed voltage when using an external resistor to ground to set the switching frequency. Pulling the pin above the PLL upper threshold causes a mode change whereby the pin becomes a synchronization input. Disabling of the internal amplifier occurs, and the pin is a high-impedance clock input to the internal PLL. If clocking edges stop, re-enabling of the internal amplifier occurs, and the mode returns to a resistor-set function. | |
| SS/TR | 4 | I | Slow-start and tracking. An external capacitor connected to this pin sets the output rise time. The voltage on this pin overrides the internal reference, allowing use of the pin for tracking and sequencing. | |
| VIN | 2 | I | Input supply voltage, 3.5 to 42 V | |
| VSENSE | 7 | I | Inverting node of the transconductance (gm) error amplifier | |
| Thermal pad | — | — | GND pin must have an electrical connection to the exposed pad on the printed-circuit board for proper operation. | |