ZHCSE52B September 2015 – May 2019 TPS57140-EP
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用范圍
- 3 說(shuō)明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Fixed Frequency PWM Control
- 7.3.2 Slope-Compensation Output Current
- 7.3.3 Bootstrap Voltage (Boot)
- 7.3.4 Low-Dropout Operation
- 7.3.5 Error Amplifier
- 7.3.6 Voltage Reference
- 7.3.7 Adjusting the Output Voltage
- 7.3.8 Enable and Adjusting UVLO
- 7.3.9 Slow-Start or Tracking Pin (SS/TR)
- 7.3.10 Overload Recovery Circuit
- 7.3.11 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
- 7.3.12 Overcurrent Protection and Frequency Shift
- 7.3.13 Selecting the Switching Frequency
- 7.3.14 How to Interface to RT/CLK Pin
- 7.3.15 Power Good (PWRGD Pin)
- 7.3.16 Overvoltage Transient Protection (OVTP)
- 7.3.17 Thermal Shutdown
- 7.3.18 Small-Signal Model for Loop Response
- 7.3.19 Simple Small-Signal Model for Peak-Current-Mode Control
- 7.3.20 Small-Signal Model for Frequency Compensation
- 7.4 Device Functional Modes
-
8 Application and Implementation
- 8.1 Application Information
- 8.2
Typical Application
- 8.2.1 Design Requirements
- 8.2.2
Detailed Design Procedure
- 8.2.2.1 Selecting the Switching Frequency
- 8.2.2.2 Output Inductor Selection (LO)
- 8.2.2.3 Output Capacitor
- 8.2.2.4 Catch Diode
- 8.2.2.5 Input Capacitor
- 8.2.2.6 Slow-Start Capacitor
- 8.2.2.7 Bootstrap Capacitor Selection
- 8.2.2.8 UVLO Set Point
- 8.2.2.9 Output Voltage and Feedback Resistors Selection
- 8.2.2.10 Compensation
- 8.2.3 Application Curves
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機(jī)械、封裝和可訂購(gòu)信息
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- DRC|10
散熱焊盤(pán)機(jī)械數(shù)據(jù) (封裝 | 引腳)
- DRC|10
訂購(gòu)信息
8.2.2.6 Slow-Start Capacitor
The slow-start capacitor determines the minimum amount of time it takes for the output voltage to reach its nominal programmed value during power up. This is useful if a load requires a controlled voltage-slew rate. This is also used if the output capacitance is very large and would require large amounts of current to charge the capacitor quickly to the output-voltage level. The large currents necessary to charge the capacitor may make the TPS57140-EP reach the current limit, or excessive current draw from the input power supply may cause the input voltage rail to sag. Limiting the output-voltage slew rate solves both of these problems.
The slow-start time must be long enough to allow the regulator to charge the output capacitor up to the output voltage without drawing excessive current. Use Equation 40 to find the minimum slow start time, tSS, necessary to charge the output capacitor, Cout, from 10% to 90% of the output voltage, Vout, with an average slow-start current of Issavg. In the example, to charge the 47-μF output capacitor up to 3.3 V while only allowing the average input current to be 0.125 A would require a 1-ms slow-start time.
After the slow-start time is known, calculate the slow-start capacitor value using Equation 6. For the example circuit, the slow-start time is not too critical, because the output capacitor value is 47 μF, which does not require much current to charge to 3.3 V. The example circuit has the slow-start time set to an arbitrary value of 1 ms, which requires a 3.3-nF capacitor.
