ZHCSE52B September 2015 – May 2019 TPS57140-EP
PRODUCTION DATA.
- 1 特性
- 2 應用范圍
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Fixed Frequency PWM Control
- 7.3.2 Slope-Compensation Output Current
- 7.3.3 Bootstrap Voltage (Boot)
- 7.3.4 Low-Dropout Operation
- 7.3.5 Error Amplifier
- 7.3.6 Voltage Reference
- 7.3.7 Adjusting the Output Voltage
- 7.3.8 Enable and Adjusting UVLO
- 7.3.9 Slow-Start or Tracking Pin (SS/TR)
- 7.3.10 Overload Recovery Circuit
- 7.3.11 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
- 7.3.12 Overcurrent Protection and Frequency Shift
- 7.3.13 Selecting the Switching Frequency
- 7.3.14 How to Interface to RT/CLK Pin
- 7.3.15 Power Good (PWRGD Pin)
- 7.3.16 Overvoltage Transient Protection (OVTP)
- 7.3.17 Thermal Shutdown
- 7.3.18 Small-Signal Model for Loop Response
- 7.3.19 Simple Small-Signal Model for Peak-Current-Mode Control
- 7.3.20 Small-Signal Model for Frequency Compensation
- 7.4 Device Functional Modes
-
8 Application and Implementation
- 8.1 Application Information
- 8.2
Typical Application
- 8.2.1 Design Requirements
- 8.2.2
Detailed Design Procedure
- 8.2.2.1 Selecting the Switching Frequency
- 8.2.2.2 Output Inductor Selection (LO)
- 8.2.2.3 Output Capacitor
- 8.2.2.4 Catch Diode
- 8.2.2.5 Input Capacitor
- 8.2.2.6 Slow-Start Capacitor
- 8.2.2.7 Bootstrap Capacitor Selection
- 8.2.2.8 UVLO Set Point
- 8.2.2.9 Output Voltage and Feedback Resistors Selection
- 8.2.2.10 Compensation
- 8.2.3 Application Curves
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
- DRC|10
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
- DRC|10
訂購信息
7.4.2 Pulse-Skip Eco-mode Control Scheme
The TPS57140-EP enters the pulse-skip mode when the voltage on the COMP pin is the minimum clamp value. The TPS57140-EP operates in a pulse-skip mode at light load currents to improve efficiency. The peak switch current during the pulse-skip mode is the greater value of either 50 mA or the peak inductor current that is a function of the minimum on-time, input voltage, output voltage, and inductance value. When the load current is low and the output voltage is within regulation, the device enters a sleep mode and draws only 116 μA of input quiescent current. While the device is in sleep mode, the output capacitor delivers the output power. As the load current decreases, the time the output capacitor supplies the load current increases and the switching frequency decreases, reducing gate-drive and switching losses. As the output voltage drops, the TPS57140-EP wakes up from sleep mode and the power switch turns on to recharge the output capacitor, see Figure 51. The internal PLL remains operating when in sleep mode. When operating at light load currents in pulse-skip mode, the switching transitions occur synchronously with the external clock signal.
Figure 51. Operation in Pulse-Skip Mode