ZHCSMV3A December 2020 – December 2021 TPS552882-Q1
PRODUCTION DATA
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 VCC Power Supply
- 7.3.2 Operation Mode Setting
- 7.3.3 Input Undervoltage Lockout
- 7.3.4 Enable and Programmable UVLO
- 7.3.5 Soft Start
- 7.3.6 Shutdown
- 7.3.7 Switching Frequency
- 7.3.8 Switching Frequency Dithering
- 7.3.9 Inductor Current Limit
- 7.3.10 Internal Charge Path
- 7.3.11 Output Voltage Setting
- 7.3.12 Output Current Indication and Cable Voltage Drop Compensation
- 7.3.13 Integrated Gate Drivers
- 7.3.14 Output Current Limit
- 7.3.15 Overvoltage Protection
- 7.3.16 Output Short Circuit Protection
- 7.3.17 Thermal Shutdown
- 7.4 Device Functional Modes
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
- RPM|26
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
- RPM|26
訂購信息
8.2.2.7 Output Current Limit Sense Resistor
The output current limit is implemented by putting a current sense resistor between the ISP and ISN pins. The value of the limit voltage between the ISP and ISN pins is 50 mV. The current sense resistor between the ISP and ISN pins should be selected to ensure that the output current limit is set high enough for output. The output current limit setting resistor is given by Equation 18.
Equation 18. 
where
- VSNS is the current limit setting voltage between the ISP and ISN pin
- IOUT_LIMIT is the desired output current limit
Because the power dissipation is large, make sure the current sense resistor has enough power dissipation capability with large package.