5 Pin Configuration and Functions

Figure 5-1 26-pin VQFN-HR RPM Transparent (Top View)

Table 5-1 Pin Functions

PIN		I/O	DESCRIPTION
NO.	NAME	I/O	DESCRIPTION
1	DR1L	O	Gate driver output for low-side MOSFET in buck side
2	DR1H	O	Gate driver output for high-side MOSFET in buck side
3	VIN	PWR	Power supply to the IC from input voltage
4	EN/UVLO	I	Enable logic input and programmable input voltage undervoltage lockout (UVLO) input. Logic high level enables the device. Logic low level disables the device and turns it into shutdown mode. After the voltage at the EN/UVLO pin is above the logic high voltage of 1.15 V, this pin acts as programmable UVLO input with 1.23-V internal reference.
5	PG	O	Power good indication. When the output voltage is above 95% of the setting output voltage, this pin outputs high impedance. When the output voltage is below 90% of the setting output voltage, this pin outputs low level
6	CC	O	Constant current output indication
7	DITH/SYNC	I	Dithering frequency setting and synchronous clock input. Use a capacitor between this pin and ground to set the dithering frequency. When this pin is short to ground or pulled above 1.2 V, there is no dithering function. An external clock can be applied at this pin to synchronize the switching frequency.
8	FSW	I	The switching frequency is programmed by a resistor between this pin and the AGND pin.
9, 24	PGND	PWR	Power ground of the IC. It is connected to the source of the low-side MOSFET.
10	AGND	PWR	Signal ground of the IC
11, 26	VOUT	PWR	Output of the buck-boost converter
12	ISP	I	Positive input of the current sense amplifier. An optional current sense resistor connected between the ISP pin and the ISN pin can limit the output current. If the sensed voltage reaches the current limit setting value in the register, a slow constant current control loop becomes active and starts to regulate the voltage between the ISP pin and the ISN pin. Connecting the ISP pin and the ISN pin together with the VOUT pin can disable the output current limit function.
13	ISN	I	Negative input of the current sense amplifier. An optional current sense resistor connected between the ISP pin and the ISN pin can limit the output current. If the sensed voltage reaches the current limit setting value in the register, a slow constant current control loop becomes active and starts to regulate the voltage between the ISP pin and the ISN pin. Connecting the ISP pin and the ISN pin together with the VOUT pin can disable the output current limit function.
14	FB	I	Connect to the center of a resistor divider to program the output voltage.
15	MODE	I	Setting the operation modes of the TPS55288x to select PFM mode or forced PWM mode in light load condition and to select the internal LDO or external 5 V for VCC by a resistor between this pin and AGND.
16	CDC	O	Voltage output proportional to the sensed voltage between the ISP pin and the ISN pin. Use a resistor between this pin and AGND to increase the output voltage to compensate voltage droop across the cable caused by the cable resistance.
17	ILIM	O	Average inductor current limit setting pin. Connect an external resistor between this pin and the AGND pin.
18	COMP	I	Output of the internal error amplifier. Connect the loop compensation network between this pin and the AGND pin.
19	VCC	O	Output of the internal regulator. A ceramic capacitor of more than 4.7 μF is required between this pin and the AGND pin.
20	BOOT2	O	Power supply for high-side MOSFET gate driver in boost side. A ceramic capacitor of 0.1 μF must be connected between this pin and the SW2 pin.
21, 25	SW2	I	The switching node pin of the boost side. It is connected to the drain of the internal low-side power MOSFET and the source of internal high-side power MOSFET.
22	BOOT1	I	Power supply for high-side MOSFET gate driver in buck side. A ceramic capacitor of 0.1 μF must be connected between this pin and the SW1 pin.
23	SW1	I	The switching node pin of the buck side. It is connected to the drain of the external low-side power MOSFET and the source of external high-side power MOSFET.