ZHCSF14D March 2010 – October 2018 TPS54260
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Fixed Frequency PWM Control
- 7.3.2 Slope Compensation Output Current
- 7.3.3 Pulse-Skip Eco-Mode
- 7.3.4 Low-Dropout Operation and Bootstrap Voltage (BOOT)
- 7.3.5 Error Amplifier
- 7.3.6 Voltage Reference
- 7.3.7 Adjusting the Output Voltage
- 7.3.8 Enable and Adjusting Undervoltage Lockout
- 7.3.9 Slow-Start / Tracking Pin (SS/TR)
- 7.3.10 Overload Recovery Circuit
- 7.3.11 Sequencing
- 7.3.12 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
- 7.3.13 Overcurrent Protection and Frequency Shift
- 7.3.14 Selecting the Switching Frequency
- 7.3.15 How to Interface to RT/CLK Pin
- 7.3.16 Powergood (PWRGD Pin)
- 7.3.17 Overvoltage Transient Protection
- 7.3.18 Thermal Shutdown
- 7.3.19 Small Signal Model for Loop Response
- 7.3.20 Simple Small Signal Model for Peak Current Mode Control
- 7.3.21 Small Signal Model for Frequency Compensation
- 7.4 Device Functional Modes
-
8 Application and Implementation
- 8.1 Application Information
- 8.2
Typical Applications
- 8.2.1
3.3-V Output Application
- 8.2.1.1 Design Requirements
- 8.2.1.2
Detailed Design Procedure
- 8.2.1.2.1 Custom Design With WEBENCH® Tools
- 8.2.1.2.2 Selecting the Switching Frequency
- 8.2.1.2.3 Output Inductor Selection (LO)
- 8.2.1.2.4 Output Capacitor
- 8.2.1.2.5 Catch Diode
- 8.2.1.2.6 Input Capacitor
- 8.2.1.2.7 Slow-Start Capacitor
- 8.2.1.2.8 Bootstrap Capacitor Selection
- 8.2.1.2.9 Undervoltage Lock Out Set Point
- 8.2.1.2.10 Output Voltage and Feedback Resistors Selection
- 8.2.1.2.11 Compensation
- 8.2.1.2.12 Discontinuous Mode and Eco-Mode Boundary
- 8.2.1.2.13 Power Dissipation Estimate
- 8.2.1.3 Application Curves
- 8.2.2 Inverting Power Supply
- 8.2.3 Split-Rail Power Supply
- 8.2.4 12-V to 3.8-V GSM Power Supply
- 8.2.5 24-V to 4.2-V GSM Power Supply
- 8.2.1
3.3-V Output Application
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
封裝選項
機械數據 (封裝 | 引腳)
散熱焊盤機械數據 (封裝 | 引腳)
訂購信息
8.2.1.2.11 Compensation
There are several methods used to compensate DC - DC regulators. The method presented here is easy to calculate and ignores the effects of the slope compensation that is internal to the device. Since the slope compensation is ignored, the actual crossover frequency will usually be lower than the crossover frequency used in the calculations. This method assumes the crossover frequency is between the modulator pole and the esr zero and the esr zero is at least 10 times greater the modulator pole. Use SwitcherPro software for a more accurate design.
To get started, the modulator pole, fpmod, and the ESR zero, fz1 must be calculated using Equation 41 and Equation 42. For Cout, use a derated value of 40 μF. Use equations Equation 43 and Equation 44, to estimate a starting point for the crossover frequency, fco, to design the compensation. For the example design, fpmod is 1206 Hz and fzmod is 530.5 kHz. Equation 43 is the geometric mean of the modulator pole and the esr zero and Equation 44 is the mean of modulator pole and the switching frequency. Equation 43 yields 25.3 kHz and Equation 44 gives 13.4 kHz. Use the lower value of Equation 43 or Equation 44 for an initial crossover frequency. For this example, a higher fco is desired to improve transient response. the target fco is 35.0 kHz. Next, the compensation components are calculated. A resistor in series with a capacitor is used to create a compensating zero. A capacitor in parallel to these two components forms the compensating pole.
To determine the compensation resistor, R4, use Equation 45. Assume the power stage transconductance, gmps, is 10.5S. The output voltage, Vo, reference voltage, VREF, and amplifier transconductance, gmea, are 3.3V, 0.8V and 310 μS, respectively. R4 is calculated to be 20.2 kΩ, use the nearest standard value of 20.0 kΩ. Use Equation 46 to set the compensation zero to the modulator pole frequency. Equation 46 yields 4740 pF for compensating capacitor C5, a 4700-pF is used for this design.
A compensation pole can be implemented if desired using an additional capacitor C8 in parallel with the series combination of R4 and C5. Use the larger value of Equation 47 and Equation 48 to calculate the C8, to set the compensation pole. C8 is not used for this design example.
