ZHCSNC8A February 2021 – March 2021 TPS541620
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| MOSFET RDS(ON) | ||||||
| RDS(on)HS | High-side FET on resistance | VBST - VSW = 5 V, TJ = 25°C | 24 | m? | ||
| RDS(on)LS | Low-side FET on resistance | BP5 = 5 V, TJ = 25°C | 10 | mΩ | ||
| tDEAD(LtoH) | Power stage driver dead-time from Low-side off to high-side on(1) | PVIN ≥ 12 V, TJ = 25°C, ILoad = 3 A | 5 | ns | ||
| tDEAD(HtoL) | Power stage driver dead-time from High-side off to low-side on(1) | PVIN ≥ 12 V, TJ = 25°C, ILoad = 3 A | 5 | ns | ||
| RSW_disch | SW discharge FET | 32 | ? | |||
| INPUT SUPPLY and CURRENT | ||||||
| VPVIN1, VPVIN2 | Power stage voltage | 4.5 | 15 | V | ||
| IVINSTBY | PVIN bias current | TJ = 25°C, EN = 5 V, non-switching | 4 | mA | ||
| IVINSTBY | PVIN standby current | TJ = 25°C, EN1 = EN2 = 0 V | 270 | μA | ||
| UNDERVOLTAGE LOCKOUT | ||||||
| VPVIN_UVLO | PVIN UVLO rising threshold | VIN slew rate 1 V/1 ms | 3.5 | 3.7 | 3.9 | V |
| VPVIN_UVLO_HYS | PVIN UVLO hysteresis | 200 | mV | |||
| VBP5 | BP5 regulation voltage | IOUT = 70 mA, PVIN ≥ 6 V | 4.8 | 5 | 5.2 | V |
| VBP5_UVLO_RI | BP5 UVLO rising voltage | 3 | V | |||
| VBP5_UVLO_FA | BP5 UVLO falling voltage | 2.7 | V | |||
| VBP5_UVLO_HYS | BP5 UVLO hysteresis | 300 | mV | |||
| VDROPOUT | LDO dropout voltage | PVIN = 4.5 V, ILOAD = 70 mA | 550 | mV | ||
| INTERNAL REFERENCE VOLTAGE | ||||||
| Feedback Voltage | Feedback voltage | TJ = 25°C | 500 | mV | ||
| Feedback accuracy | Feedback accuracy(1) | TJ = –40°C to 125°C | –1% | 1% | ||
| REMOTE SENSE AMPLIFIER | ||||||
| fUGBW | Unity gain bandwidth(1) | 12 | MHz | |||
| A0 | Open loop gain(1) | 75 | dB | |||
| SR | Slew rate(1) | 4.7 | V/μs | |||
| VICM | Input range(1) | –0.2 | 0.6 | V | ||
| VOFFSET | Input offset voltage(1) | –1.5 | 1.5 | mV | ||
| EN1 AND EN2 LOGIC THRESHOLD | ||||||
| VEN_TO_SW | Enable to start switching | PVIN > 4.5 V, toggle EN | 0.3 | ms | ||
| VEN_ON_TH | EN rising threshold | 1.2 | 1.3 | V | ||
| VEN_OFF_TH | EN falling threshold | 1 | 1.1 | V | ||
| VENHYS | EN hysteresis | 100 | mV | |||
| IEN_pullup | EN pullup current, EN floating | PVIN = 12 V | 1.4 | μA | ||
| INTERNAL BOOTSTRAP SWITCH | ||||||
| VF | BOOTSTRAP voltage drop | Iboot = 10 mA | 200 | mV | ||
| VBOOT_UVLO | BOOT UVLO | 2.3 | V | |||
| SWITCHING FREQUENCY | ||||||
| FSW | FSW1 | PVIN = 12 V, VOUT = 1.2 V | 450 | 500 | 550 | kHz |
| FSW2 | PVIN = 12 V, VOUT = 1.2 V | 900 | 1000 | 1100 | kHz | |
| FSW3 | PVIN = 12 V, VOUT = 1.2 V | 1350 | 1500 | 1650 | kHz | |
| FSW4 | PVIN = 12 V, VOUT = 1.2 V | 1800 | 2000 | 2200 | kHz | |
| ton_min | SW1, SW2 minimum controllable on-time | 40 | 50 | ns | ||
| toff_min | SW1, SW2 minimum controllable off time | 150 | 200 | ns | ||
| SYNCHRONIZATION | ||||||
| VIH(SYNC) | High-level input | 2 | V | |||
| VIL(SYNC) | Low-level input | 0.6 | V | |||
| DSYNC | Input duty cycle | 20% | 80% | |||
| FSYNC to SW | Sync to SW variation, % from sync to SW(1) | –20% | +20% | |||
| VCLKOHigh | CLKO high-level output | Io = 20 μA, Cload = 20 pF | 2.2 | V | ||
| VCLKOLow | CLKO low-level output | Io = 20 μA, Cload = 20 pF | 0.4 | V | ||
| tPSW(CLKO) | Pulsewidth output | Cload = 20 pF | 80 | ns | ||
| PRIMARY PHASE SHIFT | ||||||
| tSW12SW2 | Phase delay from SW1 to SW2 | 180 | ° | |||
| tSYNC2SW1(P) | Phase primary SYNC IN to SW1 delay in 2-phase | 216 | ns | |||
| SECONDARY PHASE SHIFT | ||||||
| tSYNC2SW1(S) | Phase delay from SYNC IN to SW1 | 90 | ° | |||
| tSYNC2SW1(S) | Phase delay from SYNC IN to SW2 | 270 | ° | |||
| HIGH SIDE CURRENT DETECTION | ||||||
| IHSOC | High-side current limit, peak inductor current | 12 VIN, 1 VOUT, 1 MHz | 8.0 | 9.5 | 11.5 | A |
| LOW SIDE CURRENT DETECTION | ||||||
| ILSOC | Low-side current limit, valley inductor current | 12 VIN, 1 VOUT, 1 MHz | 6.2 | 6.8 | 9.0 | A |
| ILSNOC | Low-side negative current limit, valley inductor current | 12 VIN, 1 VOUT, 1 MHz | -4.2 | -3.5 | -2.8 | A |
| Low Side Zero Cross | Low-side zero cross | 250 | mA | |||
| tENTER_HICCUP | OCP hiccup entry time | 16 | cycles | |||
| tHICDLY | Hiccup delay time | Tss = 1 ms | 7 | ms | ||
| OV / UV PROTECTION | ||||||
| VOVP | Overvoltage threshold | 120% | ||||
| tOVPDLY | OVP response time(1) | 10 | μs | |||
| VUVP | Undervoltage threshold | 80% | ||||
| tUVPDLY | UVP response time(1) | 16 | cycles | |||
| THERMAL SHUTDOWN | ||||||
| TSDN | Built-in thermal shutdown threshold(1) | 165 | °C | |||
| TSDN_HYS | Built-in thermal shutdown hysteresis(1) |
20 | °C | |||
| INTERNAL SOFT START | ||||||
| tSS_single-output | Soft-start time (from switching to PGOOD high) | Without CSS | 1 | ms | ||
| tSS_dual-output | Soft-start time (from switching to PGOOD high) | Fixed | 1 | ms | ||
| EXTERNAL SOFT START | ||||||
| IC_tSS | CSS charge current | Tss <= 50 ms, Css < 0.3 μF | 2 | μA | ||
| RSS | Soft-start discharge FET | 600 | ? | |||
| CURRENT SHARE ACCURACY | ||||||
| ISHARE(acc) | Output current sharing accuracy, defined as the ratio of the current difference between channels to total current(sensing error only)(1) | Load ≥ 0.5 × 6 A | 15% | |||
| ISHARE(acc) | Output current sharing accuracy, defined as the ratio of the current difference between channels to total current(sensing error only)(1) | Load < 0.5 × 6 A | 1 | A | ||
| VISHARE_L | Fault voltage falling | 200 | mV | |||
| VISHARE_L | Fault voltage rising | 300 | mV | |||
| POWER GOOD COMPARATOR | ||||||
| VPG(thresh) | Power good threshold (%VFB) | FB falling, PG high to low | 87% | 90% | 93% | |
| VPG(thresh) | Power good threshold (%VFB) | FB rising, PG low to high | 90% | 93% | 96% | |
| VPG(thresh) | Power good threshold (%VFB) | FB rising, PG high to low | 107% | 110% | 113% | |
| VPG(thresh) | Power good threshold (%VFB) | FB falling, PG low to high | 104% | 107% | 110% | |
| IPGD_lkg | PGOOD1, PGOOD2 leakage current | V(PGOOD1) = V(PGOOD2) = 5.5 V | 1 | μA | ||
| tPGDLY | Delay for PGOOD low to high | 50 | μs | |||
| tPGDLY | Delay for PGOOD high to low | 10 | μs | |||
| VPGDLOW | PGOOD output low voltage | VIN = 4 V, VOUT = 0 V, IPGOOD = 6 mA | 0.4 | V | ||
| VMINVIN_OUTPUT | Minimum PVIN for asserted output | VPGOOD ≤ 0.4V | 1.5 | V | ||