ZHCSIJ7A July 2018 – October 2021 TPS3431
PRODUCTION DATA
The Enable (EN) input allows a processor or other logic circuits to initiate a single cycle watchdog reset by momentarily bringing Enable low, or a permanent disable by keeping Enable low. After EN goes to a logic high and VDD is above VDD (min), ENOUT and WDO go logic high after the watchdog reset delay time (tRST). If EN is not controlled externally, then EN can either be connected to VDD or left floating because the EN pin is internally pulled up to VDD. When EN is forced logic low, ENOUT goes low after a propagation delay of 200 ns and WDO goes high impedance and pulls to logic high due to the external pull-up resistor. Because WDO and ENOUT are both open-drain outputs, these outputs can be tied together to create an OR logic function so that if either output pulls down to logic low, the other will also pull down logic low.