ZHCSIJ8A July 2018 – October 2021 TPS3431-Q1
PRODUCTION DATA
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Detailed Description
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- DRB|8
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- DRB|8
訂購信息
7.3.2.2 Watchdog Input WDI
WDI is the watchdog timer input that controls the WDO output. The WDI input is triggered by the falling edge of the input signal. To ensure proper functionality of the watchdog timer, always issue the WDI pulse before tWD(min). If the pulse is issued in this region, then WDO remains unasserted. Otherwise, the device asserts WDO, putting the WDO pin into a low-impedance state therefore WDO will be logic low.
The watchdog input (WDI) is a digital pin. To ensure there is no increase in IDD, drive the WDI pin to either VDD or GND at all times. Putting the pin to an intermediate voltage can cause an increase in supply current (IDD) because of the architecture of the digital logic gates. When EN is logic low, the watchdog is disabled and all signals input to WDI are ignored. When EN is logic high, the device resumes normal operation and no longer ignores the signal on WDI. If the watchdog is disabled, drive the WDI pin to either VDD or GND. Figure 7-1 shows the valid region for a WDI pulse to be issued to prevent WDO from being triggered and pulled low.
Figure 7-1 Watchdog Timing Diagram