ZHCSIJ8A July 2018 – October 2021 TPS3431-Q1
PRODUCTION DATA
| PARAMETER | DESIGN REQUIREMENT | DESIGN RESULT |
|---|---|---|
| Watchdog disable for initialization period | Watchdog must remain disabled for 5 seconds until logic enables the watchdog timer | 5.02 seconds (typ) |
| Programmable disable feature | Microcontroller controls SET1 on TPS3431 via a GPIO | The Microcontroller can disable TPS3431 via SET1 and thus disable the watchdog for any reason. |
| Output logic voltage | 1.8-V Open-Drain | 1.8V Open-Drain |
| Monitored rail (TPS3890) | 1.8 V with a 5% threshold and 1% accuracy | Worst-case VITN = 1.714 V – 4.7% |
| Watchdog timeout (TPS3431) | 265 ms typical | tWD(min) = 213 ms, tWD(TYP) = 264 ms, tWD(max) = 319 ms |
| Maximum device current consumption | 50 μA | 37 μA when WDO is asserted |