ZHCSL91B October 2020 – March 2022 TPS25947
PRODUCTION DATA
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 Revision History
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 Input Reverse Polarity Protection
- 8.3.2 Undervoltage Lockout (UVLO and UVP)
- 8.3.3 Overvoltage Lockout (OVLO)
- 8.3.4 Overvoltage Clamp (OVC)
- 8.3.5 Inrush Current, Overcurrent, and Short Circuit Protection
- 8.3.6 Analog Load Current Monitor
- 8.3.7 Reverse Current Protection
- 8.3.8 Overtemperature Protection (OTP)
- 8.3.9 Fault Response and Indication (FLT)
- 8.3.10 Auxiliary Channel Control (AUXOFF)
- 8.3.11 Power Good Indication (PG)
- 8.4 Device Functional Modes
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
- RPW|10
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
訂購信息
8.3.11 Power Good Indication (PG)
The TPS259472x, TPS259474x variants provide an active high digital output (PG) which serves as a power good indication signal and is asserted high depending on the voltage at the PGTH pin along with the device state information. The PG is an open-drain pin and must be pulled up to an external supply.
After power up, PG is pulled low initially. The device initiates a inrush sequence in which the HFET is turned on in a controlled manner. When the HFET gate voltage reaches the full overdrive indicating that the inrush sequence is complete and the voltage at PGTH is above VPGTH(R), the PG is asserted after a de-glitch time (tPGA).
PG is de-asserted if at any time during normal operation, the voltage at PGTH falls below VPGTH(F), or the device detects a fault (except overcurrent). The PG de-assertion de-glitch time is tPGD.
Figure 8-17 TPS259472x, TPS259474x PG Timing
Diagram|
Event |
Protection Response |
PG Pin |
PG Delay |
|---|---|---|---|
Undervoltage (UVP or UVLO) | Shutdown | L | |
Input Reverse Polarity | Shutdown | L | |
Overvoltage (OVC) (TPS259472x only) | Clamp | H (If PGTH pin voltage > VPGTH(R)) L (If PGTH pin voltage < VPGTH(F)) | tPGA tPGD |
Overvoltage (OVLO) (TPS259474x only) | Shutdown | L (If PGTH pin voltage < VPGTH(F)) | tPGD |
Steady State | NA | H (If PGTH pin voltage > VPGTH(R)) L (If PGTH pin voltage < VPGTH(F)) | tPGA tPGD |
Transient overcurrent | NA | H (If PGTH pin voltage > VPGTH(R)) L (If PGTH pin voltage < VPGTH(F)) | tPGA tPGD |
Persistent overload (TPS259472x only) | Current Limiting | H (If PGTH pin voltage > VPGTH(R)) L (If PGTH pin voltage < VPGTH(F)) | tPGA tPGD |
Persistent overload (TPS259474x only) | Shutdown | L | |
Output Short-Circuit to GND | Fast trip followed by Current Limit | H (If PGTH pin voltage > VPGTH(R)) L (If PGTH pin voltage < VPGTH(F)) | tPGA tPGD |
ILM Pin Open | Shutdown | L (If PGTH pin voltage < VPGTH(F)) | tPGD |
ILM Pin Shorted to GND | Shutdown | L (If PGTH pin voltage < VPGTH(F)) | tPGD |
Reverse current ((VOUT – VIN) > VREVTH) | Reverse current blocking | L | tPGD |
Overtemperature | Shutdown | L |
When there is no supply to the device, the PG pin is expected to stay low. However, there is no active pull-down in this condition to drive this pin all the way down to 0 V. If the PG pin is pulled up to an independent supply which is present even if the device is unpowered, there can be a small voltage seen on this pin depending on the pin sink current, which is a function of the pull-up supply voltage and resistor. Minimize the sink current to keep this pin voltage low enough not to be detected as a logic HIGH by associated external circuits in this condition.