ZHCSNR4B May 2021 – April 2022 TPS25946
PRODUCTION DATA
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 Revision History
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 Undervoltage Lockout (UVLO and UVP)
- 8.3.2 Overvoltage Lockout (OVLO)
- 8.3.3 Inrush Current, Overcurrent, and Short-Circuit Protection
- 8.3.4 Analog Load Current Monitor
- 8.3.5 Reverse Current Protection
- 8.3.6 Overtemperature Protection (OTP)
- 8.3.7 Fault Response and Indication (FLT)
- 8.3.8 Power Good Indication (PG)
- 8.3.9 Input Supply Good Indication (SPLYGD)
- 8.4 Device Functional Modes
-
9 Application and Implementation
- 9.1 Application Information
- 9.2
Typical Application
- 9.2.1 Design Requirements
- 9.2.2
Detailed Design Procedure
- 9.2.2.1 Device Selection
- 9.2.2.2 Setting Overvoltage Threshold
- 9.2.2.3 Setting Output Voltage Rise Time (tR)
- 9.2.2.4 Setting Power Good Assertion Threshold
- 9.2.2.5 Setting Overcurrent Threshold (ILIM)
- 9.2.2.6 Setting Overcurrent Blanking Interval (tITIMER)
- 9.2.2.7 Selecting External Bias Resistor (R5)
- 9.2.2.8 Selecting External Diode (D1)
- 9.2.3 Application Curve
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RPW|10
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
訂購信息
8.3.8 Power Good Indication (PG)
The TPS259460x variants provide an active high digital output (PG) which serves as a power good indication signal and is asserted high depending on the voltage at the PGTH pin along with the device state information. The PG is an open-drain pin and must be pulled up to an external supply.
After power up, PG is pulled low initially. The device initiates a inrush sequence in which the HFET is turned on in a controlled manner. When the HFET gate voltage reaches the full overdrive indicating that the inrush sequence is complete and the voltage at PGTH is above VPGTH(R), the PG is asserted after a de-glitch time (tPGA).
PG is de-asserted if at any time during normal operation, the voltage at PGTH falls below VPGTH(F) or the device detects a fault (except overcurrent). The PG de-assertion de-glitch time is tPGD.
Figure 8-9 TPS259460x PG Timing DiagramEvent | Protection Response | PG Pin Status | PG Delay |
|---|---|---|---|
Undervoltage (UVP or UVLO) | Shutdown | L | |
Overvoltage (OVLO) | Shutdown | L (If PGTH pin voltage < VPGTH(F)) | tPGD |
Steady State | NA | H (If PGTH pin voltage > VPGTH(R)) L (If PGTH pin voltage < VPGTH(F)) | tPGA tPGD |
Transient overcurrent | NA | H (If PGTH pin voltage > VPGTH(R)) L (If PGTH pin voltage < VPGTH(F)) | tPGA tPGD |
Persistent overload in forward direction (IN to OUT) | Current Limiting | H (If PGTH pin voltage > VPGTH(R)) L (If PGTH pin voltage < VPGTH(F)) | tPGA tPGD |
OUT Pin Short-Circuit to GND | Fast-trip followed by Current Limit | H (If PGTH pin voltage > VPGTH(R)) L (If PGTH pin voltage < VPGTH(F)) | tPGA tPGD |
ILM Pin Open | Shutdown | L (If PGTH pin voltage < VPGTH(F)) | tPGD |
ILM Pin Shorted to GND | Shutdown | L (If PGTH pin voltage < VPGTH(F)) | tPGD |
Overtemperature | Shutdown | L |
When there is no supply to the device, the PG pin is expected to stay low. However, there is no active pulldown in this condition to drive this pin all the way down to 0 V. If the PG pin is pulled up to an independent supply which is present even if the device is unpowered, there can be a small voltage seen on this pin depending on the pin sink current, which is a function of the pullup supply voltage and resistor. Minimize the sink current to keep this pin voltage low enough not to be detected as a logic HIGH by associated external circuits in this condition.