For all applications, a 0.1-uF or greater ceramic decoupling capacitor is recommended between IN terminal and GND. For hot-plug applications, where input power path inductance is negligible, this capacitor can be eliminated/minimized.
The optimum placement of decoupling capacitor is closest to the IN and GND terminals of the device. Care must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN terminal, and the GND terminal of the IC. See Figure 12-1 for a PCB layout example.
High current carrying power path connections must be as short as possible and must be sized to carry at least twice the full-load current.
Low current signal ground (SGND), which is the reference ground for the device must be a copper plane or island.
Locate all TPS25940xx-Q1 support components: R(ILIM), CdVdT, R(IMON), and resistors for UVLO and OVP, close to their connection pin. Connect the other end of the component to the SGND with shortest trace length.
The trace routing for the RILIM and R(IMON) components to the device must be as short as possible to reduce parasitic effects on the current limit and current monitoring accuracy. These traces must not have any coupling to switching signals on the board.
The SGND plane must be connected to high current ground (main power ground) at a single point, that is at the negative terminal of input capacitor.
Protection devices such as TVS, snubbers, capacitors, or diodes must be placed physically close to the device they are intended to protect, and routed with short traces to reduce inductance. For example, a protection Schottky diode is recommended to address negative transients due to switching of inductive loads, and it must be physically close to the OUT pins.
Thermal Considerations: When properly mounted the PowerPAD? package provides significantly greater cooling ability than an ordinary package. To operate at rated power, the PowerPAD must be soldered directly to the board GND plane directly under the device. The PowerPAD is at GND potential and can be connected using multiple vias to inner layer GND. Other planes, such as the bottom side of the circuit board can be used to increase heat sinking in higher current applications. See the Technical Briefs, PowerPad? Thermally Enhanced Package, SLMA002) and PowerPAD? Made Easy, SLMA004) for more information on using this PowerPAD? package.
The thermal via land pattern specific to TPS25940xx-Q1 can be downloaded from the TPS25940 device webpage.
Obtaining acceptable performance with alternate layout schemes is possible; however this layout has been shown to produce good results and is intended as a guideline.