ZHCSCE7I March 2014 – July 2019 TPS23861
PRODUCTION DATA.
Command = 1Ah with 1 Data Byte, Write Only
| BITS | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
|---|---|---|---|---|---|---|---|---|
| BIT NAME | CLRAIN | CLINP | RESAL | RESP4 | RESP3 | RESP2 | RESP1 |
Push button register.
Writing a “1” at a bit location triggers an event while a “0” has no impact.
NOTE
A reset port write command to 0x1A requires an I2C bus processing delay of 1.2 ms when followed by a Detect/Class Enable (0x14) write command. This delay applies from the end of the reset port command (stop pulse) to the end of the Detect/Class Enable command (stop pulse).
Bit Descriptions
CLRAIN: Clear all interrupts bit. Writing a “1” to CLRAIN clears all event registers and all bits in the Interrupt Register. It also releases the INT pin.
CLINP: When a “1” is written to this register, the TPS23861 releases the INT pin without any impact on either the event registers nor on the Interrupt Register.
RESAL: Reset register bits when a “1” is written to this location. Writing a “1” to this location results in a state equivalent to a power-up reset.
NOTE
For any port with power enable set (PEx=1 in 0x10), ensure that port power good status in 0x10 is also set (PGx=1) prior to writing a reset port command to the Reset register (0x1A).
NOTE
The VDUV and VPUV bits (Supply Event Register) follow the state of VDD and VPWR supply rails.
RESP4-RESP1: Reset port bits. Used to force an immediate port(s) turn off in any mode, by writing a “1” at the corresponding RESPn bit location(s). When port n is reset, the following takes place.