ZHCSCE7I March 2014 – July 2019 TPS23861
PRODUCTION DATA.
- 1 特性
- 2 應用范圍
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Detection Resistance Measurement
- 7.3.2 Physical Layer Classification
- 7.3.3 Class and Detect Fields
- 7.3.4 Register State Following a Fault
- 7.3.5 Disconnect
- 7.3.6 Disconnect Threshold
- 7.3.7 Fast Shutdown Mode
- 7.3.8 Legacy Device Detection
- 7.3.9 VPWR Undervoltage and UVLO Events
- 7.3.10 Timer-Deferrable Interrupt Support
- 7.3.11 A/D Converter and I2C Interface
- 7.3.12 Independent Operation when the AUTO Bit is Set
- 7.3.13 I2C Slave Address and AUTO Bit Programming
- 7.4 Device Functional Modes
- 7.5
Register Map – I2C-Addressable
- 7.5.1 Interrupt Register
- 7.5.2 Interrupt Enable Register
- 7.5.3 Power Event Register
- 7.5.4 Detection Event Register
- 7.5.5 Fault Event Register
- 7.5.6 Start/ILIM Event Register
- 7.5.7 Supply Event Register
- 7.5.8 Port n Status Register
- 7.5.9 Power Status Register
- 7.5.10 I2C Slave Address Register
- 7.5.11 Operating Mode Register
- 7.5.12 Disconnect Enable Register
- 7.5.13 Detect/Class Enable Register
- 7.5.14 Port Power Priority Register
- 7.5.15 Timing Configuration Register
- 7.5.16 General Mask 1 Register
- 7.5.17 Detect/Class Restart Register
- 7.5.18 Power Enable Register
- 7.5.19 Reset Register
- 7.5.20 Legacy Detect Mode Register
- 7.5.21 Two-Event Classification Register
- 7.5.22 Interrupt Timer Register
- 7.5.23 Disconnect Threshold Register
- 7.5.24 ICUTnm CONFIG Register
- 7.5.25 Temperature Register
- 7.5.26 Input Voltage Register
- 7.5.27 Port n Current Register
- 7.5.28 Port n Voltage Register
- 7.5.29 PoE Plus Register
- 7.5.30 Firmware Revision Register
- 7.5.31 I2C Watchdog Register
- 7.5.32 Device ID Register
- 7.5.33 Cool Down/Gate Drive Register
- 7.5.34 Port n Detect Resistance Register
- 7.5.35 Port n Detect Voltage Difference Register
- 7.5.36 Reserved Registers
-
8 Application and Implementation
- 8.1 Introduction to PoE
- 8.2 Application Information
- 8.3 Typical Application
- 8.4 System Examples
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
6.6 Timing Requirements
–40 ≤ TJ ≤ +125°C, VVDD = 3.3 V, VVPWR = 48 V, VDGND = VAGND, DGND, KSENSA and KSENSB connected to AGND, and all outputs are unloaded, PoEPn = 0, Positive currents are into pins, RS = 0.255 Ω, to KSENSA (SEN1 or SEN2) or to KSENSB (SEN3 or SEN4), RSENS = 22 Ω, RDRAIN = 47 Ω, typical values are at 25°C. All voltages are with respect to AGND, operating registers loaded with default values (unless otherwise noted)| MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|
| fSCL | SCL clock frequency | 10 | 400 | kHz | |
| tLOW | LOW period of SCL clock | 1.3 | µs | ||
| tHIGH | HIGH period of SCL clock | 0.6 | µs | ||
| tfo | SDAO output fall time, SDAO, 2.3 → 0.8 V, Cb = 10 pF, 10-kΩ pullup to 3.3 V | 21 | 250 | ns | |
| SDAO output fall time, SDAO, 2.3 → 0.8 V, Cb = 400 pF, 1.3-kΩ pullup to 3.3 V | 60 | 250 | ns | ||
| CI2C | SCL capacitance | 10 | pF | ||
| CI2C_SDA | SDAI, SDAO capacitance | 6 | pF | ||
| tSU,DATW | Data set-up time (write operation) | 100 | ns | ||
| tSU,DATR | Data set-up time (read operation), SDAO, 2.3 ↔ 0.8 V, Cb = 400 pF, 1.3-kΩ pull up to 3.3 V | 600 | ns | ||
| tHD,DATW | Data hold time (write operation) | 0 | ns | ||
| tHD,DATR | Data hold time (read operation) | 150 | 600 | ns | |
| tfSDA | Input fall times of SDAI, 2.3 → 0.8 V | 20 | 250 | ns | |
| trSDA | Input rise times of SDAI, 0.8 → 2.3 V | 20 | 300 | ns | |
| tr | Input rise time of SCL, 0.8 → 2.3 V | 20 | 300 | ns | |
| tf | Input fall time of SCL, 2.3 → 0.8 V | 20 | 200 | ns | |
| tBUF | Bus free time between a stop and start condition | 1.3 | µs | ||
| tHD,STA | Hold time after (repeated) start condition | 0.6 | µs | ||
| tSU,STA | Repeated start condition set-up time | 0.6 | µs | ||
| tSU,STO | Stop condition set-up time | 0.6 | µs | ||
| tFLT_INT(1) | Fault to INT assertion, Time to internally register an interrupt in response to a fault | 150 | µs | ||
| tARA_INT | ARA to INT negation | 500 | ns | ||
| tDG | Suppressed spike pulse width, SDAI and SCL | 50 | ns | ||
| tRDG | RESET input minimum pulse width (deglitch time) | 5 | µs | ||
| tWDT_I2C | I2C Watchdog trip delay | 1.1 | 2.2 | 3.3 | s |
| tSTP_AOUT | Delay STOP bit to AOUT high during I2C address programming | 1.25 | µs | ||
(1) These parameters are provided for reference only, and do not constitute part of TI's published specifications for purposes of TI's product warranty.
Figure 1. I2C Timings