ZHCSCE7I March 2014 – July 2019 TPS23861
PRODUCTION DATA.
| MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|
| fSCL | SCL clock frequency | 10 | 400 | kHz | |
| tLOW | LOW period of SCL clock | 1.3 | µs | ||
| tHIGH | HIGH period of SCL clock | 0.6 | µs | ||
| tfo | SDAO output fall time, SDAO, 2.3 → 0.8 V, Cb = 10 pF, 10-kΩ pullup to 3.3 V | 21 | 250 | ns | |
| SDAO output fall time, SDAO, 2.3 → 0.8 V, Cb = 400 pF, 1.3-kΩ pullup to 3.3 V | 60 | 250 | ns | ||
| CI2C | SCL capacitance | 10 | pF | ||
| CI2C_SDA | SDAI, SDAO capacitance | 6 | pF | ||
| tSU,DATW | Data set-up time (write operation) | 100 | ns | ||
| tSU,DATR | Data set-up time (read operation), SDAO, 2.3 ↔ 0.8 V, Cb = 400 pF, 1.3-kΩ pull up to 3.3 V | 600 | ns | ||
| tHD,DATW | Data hold time (write operation) | 0 | ns | ||
| tHD,DATR | Data hold time (read operation) | 150 | 600 | ns | |
| tfSDA | Input fall times of SDAI, 2.3 → 0.8 V | 20 | 250 | ns | |
| trSDA | Input rise times of SDAI, 0.8 → 2.3 V | 20 | 300 | ns | |
| tr | Input rise time of SCL, 0.8 → 2.3 V | 20 | 300 | ns | |
| tf | Input fall time of SCL, 2.3 → 0.8 V | 20 | 200 | ns | |
| tBUF | Bus free time between a stop and start condition | 1.3 | µs | ||
| tHD,STA | Hold time after (repeated) start condition | 0.6 | µs | ||
| tSU,STA | Repeated start condition set-up time | 0.6 | µs | ||
| tSU,STO | Stop condition set-up time | 0.6 | µs | ||
| tFLT_INT(1) | Fault to INT assertion, Time to internally register an interrupt in response to a fault | 150 | µs | ||
| tARA_INT | ARA to INT negation | 500 | ns | ||
| tDG | Suppressed spike pulse width, SDAI and SCL | 50 | ns | ||
| tRDG | RESET input minimum pulse width (deglitch time) | 5 | µs | ||
| tWDT_I2C | I2C Watchdog trip delay | 1.1 | 2.2 | 3.3 | s |
| tSTP_AOUT | Delay STOP bit to AOUT high during I2C address programming | 1.25 | µs | ||
Figure 1. I2C Timings