ZHCSPB6E July 2022 – April 2025 TPS1211-Q1
PRODUCTION DATA
- 1
- 1 特性
- 2 應用
- 3 說明
- 4 Device Comparison Table
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Parameter Measurement Information
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 Charge Pump and Gate Driver Output (VS, PU, PD, BST, SRC)
- 8.3.2 Capacitive Load Driving
- 8.3.3 Overcurrent and Short-Circuit Protection
- 8.3.4 Analog Current Monitor Output (IMON)
- 8.3.5 Overvoltage (OV) and Undervoltage Protection (UVLO)
- 8.3.6 Remote Temperature Sensing and Protection (DIODE)
- 8.3.7 Output Reverse Polarity Protection
- 8.3.8 TPS1211x-Q1 as a Simple Gate Driver
- 8.4 Device Functional Modes
- 9 Application and Implementation
- 10Device and Documentation Support
- 11Revision History
- 12Mechanical, Packaging, and Orderable Information
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
- DGX|19
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
訂購信息
8.3.7 Output Reverse Polarity Protection
The TPS1211x-Q1 withstands output reverse
voltages down to -30 V. With INP low, PD is pulled low to SRC and keeps the external FET
OFF even with output (SRC) voltage at negative levels preventing high current flow and
protecting the main FET. Refer to Figure 8-16 and Figure 8-17 for test
waveforms.
Figure 8-16 Output Short to -30 V
Response with VIN = 0 V and INP = LOW
Figure 8-17 Output Short to -30 V
Response with VIN = 12 V and INP = LOW
Figure 8-16 Output Short to -30 V
Response with VIN = 0 V and INP = LOWFigure 8-17 Output Short to -30 V
Response with VIN = 12 V and INP = LOW