ZHCSPB6E July 2022 – April 2025 TPS1211-Q1
PRODUCTION DATA
- 1
- 1 特性
- 2 應用
- 3 說明
- 4 Device Comparison Table
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Parameter Measurement Information
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 Charge Pump and Gate Driver Output (VS, PU, PD, BST, SRC)
- 8.3.2 Capacitive Load Driving
- 8.3.3 Overcurrent and Short-Circuit Protection
- 8.3.4 Analog Current Monitor Output (IMON)
- 8.3.5 Overvoltage (OV) and Undervoltage Protection (UVLO)
- 8.3.6 Remote Temperature Sensing and Protection (DIODE)
- 8.3.7 Output Reverse Polarity Protection
- 8.3.8 TPS1211x-Q1 as a Simple Gate Driver
- 8.4 Device Functional Modes
- 9 Application and Implementation
- 10Device and Documentation Support
- 11Revision History
- 12Mechanical, Packaging, and Orderable Information
8.3.2.1 FET Gate Slew Rate Control
For limiting inrush current during turn-ON of the FET with capacitive loads, use R1, R2, C1 as shown in Figure 8-6. The R1 and C1 components slow down the voltage ramp rate at the gate of the FET. The FET source follows the gate voltage resulting in a controlled voltage ramp across the output capacitors.
Figure 8-6 Inrush Current Limiting with
FET Gate Slew Rate ControlUse the Equation 2 to calculate the inrush current during turn-ON of the FET.
Where,
CLOAD is the load capacitance, VBATT is the input voltage and Tcharge is the charge time, V(BST-SRC) is the charge pump voltage (12 V),
Use a damping resistor R2 (~ 10 Ω) in series with C1. Equation 3 can be used to compute required C1 value for a target inrush current. A 100-kΩ resistor for R1 can be a good starting point for calculations.
Connecting PD pin of TPS1211x-Q1 directly to the gate of the external FET ensures fast turn-OFF without any impact of R1 and C1 components.
C1 results in an additional loading on CBST to charge during turn-ON. Use Equation 4 to calculate the required CBST value.
