ZHCSG96A May 2017 – May 2019 TMP116
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagrams
- 7.3 Feature Description
- 7.4 Device Functional Modes
- 7.5
Programming
- 7.5.1 EEPROM Programming
- 7.5.2 Pointer Register
- 7.5.3 I2C and SMBus Interface
- 7.6
Registers Map
- 7.6.1
Register Descriptions
- 7.6.1.1 Temperature Register (address = 00h) [default reset = 8000h]
- 7.6.1.2 Configuration Register (address = 01h) [Factory default reset = 0220h]
- 7.6.1.3 High Limit Register (address = 02h) [Factory default reset = 6000h]
- 7.6.1.4 Low Limit Register (address = 03h) [Factory default reset = 8000h]
- 7.6.1.5 EEPROM Unlock Register (address = 04h) [reset = 0000h]
- 7.6.1.6 EEPROM1 Register (address = 05h) [reset = XXXXh]
- 7.6.1.7 EEPROM2 Register (address = 06h) [reset = XXXXh]
- 7.6.1.8 EEPROM3 Register (address = 07h) [reset = 0000h]
- 7.6.1.9 EEPROM4 Register (address = 08h) [reset = XXXXh]
- 7.6.1.10 Device ID Register (address = 0Fh) [reset = 1116h]
- 7.6.1
Register Descriptions
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
7.4.2.2 Therm Mode
When the T/nA bit in the configuration register is set to 1 the device is in therm mode. In this mode, the device compares the conversion result at the end of every conversion with the values in the low limit register and high limit register and sets the HIGH_Alert status flag in the configuration register if the temperature exceeds the value in the high limit register. When set, the device clears the HIGH_Alert status flag if the conversion result goes below the value in the low limit register. Thus, the difference between the high and low limits effectively acts like a hysteresis. In this mode, the LOW_Alert status flag is disabled and always reads 0. Unlike the alert mode, I2C reads of the configuration register do not affect the status bits. The HIGH_Alert status flag is only set or cleared at the end of conversions based on the value of the temperature result compared to the high and low limits.
As in alert mode, configuring the device in therm mode also affects the behaviour of the ALERT pin. In this mode, the device asserts the ALERT pin if the HIGH_Alert status flag is set and deasserts the ALERT pin when the HIGH_Alert status flag is cleared. In therm mode, the ALERT pin cannot be cleared by performing an I2C read of the configuration register or by performing an SMBus alert response command. As in alert mode, the polarity of the active state of the ALERT pin can be changed by using the POL bit setting in the configuration register.
Thus, this mode effectively makes the device behave like a high-limit threshold detector and can be used in applications where detecting if the temperature has gone above a desired threshold is needed. Figure 24 shows a timing diagram of this mode.
Figure 24. Therm Mode Timing Diagram