ZHCSG96A May 2017 – May 2019 TMP116
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagrams
- 7.3 Feature Description
- 7.4 Device Functional Modes
- 7.5
Programming
- 7.5.1 EEPROM Programming
- 7.5.2 Pointer Register
- 7.5.3 I2C and SMBus Interface
- 7.6
Registers Map
- 7.6.1
Register Descriptions
- 7.6.1.1 Temperature Register (address = 00h) [default reset = 8000h]
- 7.6.1.2 Configuration Register (address = 01h) [Factory default reset = 0220h]
- 7.6.1.3 High Limit Register (address = 02h) [Factory default reset = 6000h]
- 7.6.1.4 Low Limit Register (address = 03h) [Factory default reset = 8000h]
- 7.6.1.5 EEPROM Unlock Register (address = 04h) [reset = 0000h]
- 7.6.1.6 EEPROM1 Register (address = 05h) [reset = XXXXh]
- 7.6.1.7 EEPROM2 Register (address = 06h) [reset = XXXXh]
- 7.6.1.8 EEPROM3 Register (address = 07h) [reset = 0000h]
- 7.6.1.9 EEPROM4 Register (address = 08h) [reset = XXXXh]
- 7.6.1.10 Device ID Register (address = 0Fh) [reset = 1116h]
- 7.6.1
Register Descriptions
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機(jī)械、封裝和可訂購(gòu)信息
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- DRV|6
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- DRV|6
訂購(gòu)信息
6.6 Two-Wire Interface Timing
minimum and maximum specifications are over –55°C to 125°C and V+ = 1.9 V to 5.5 V (unless otherwise noted); typical specifications are at TA = 25°C and V+ = 3.3 V; values are based on statistical analysis of samples tested during initial release| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| fSCL | SCL operating frequency | 1 | 400 | kHz |
| tBUF | Bus free time between STOP and START conditions | 1300 | ns | |
| tHD;STA | Hold time after repeated START condition.
After this period, the first clock is generated. |
600 | ns | |
| tSU;STA | Repeated START condition setup time | 600 | ns | |
| tSU;STO | STOP condition setup time | 600 | ns | |
| tHD;DAT | Data hold time | 0 | ns | |
| tVD;DAT | Data valid time(1) | 0.9 | µs | |
| tSU;DAT | Data setup time | 100 | ns | |
| tLOW | SCL clock low period | 1300 | ns | |
| tHIGH | SCL clock high period | 600 | ns | |
| tF – SDA | Data fall time | 20 × (V+ / 5.5) | 300 | ns |
| tF, tR – SCL | Clock fall and rise time | 300 | ns | |
| tR | Rise time for SCL ≤ 100 kHz | 1000 | ns | |
| Serial bus timeout (SDA bus released if there is no clock) | 20 | 40 | ms | |
(1) tVD;DATA = time for data signal from SCL low to SDA output (high to low, depending on which is worse).
Figure 1. Two-Wire Timing Diagram