ZHCSG96A May 2017 – May 2019 TMP116
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagrams
- 7.3 Feature Description
- 7.4 Device Functional Modes
- 7.5
Programming
- 7.5.1 EEPROM Programming
- 7.5.2 Pointer Register
- 7.5.3 I2C and SMBus Interface
- 7.6
Registers Map
- 7.6.1
Register Descriptions
- 7.6.1.1 Temperature Register (address = 00h) [default reset = 8000h]
- 7.6.1.2 Configuration Register (address = 01h) [Factory default reset = 0220h]
- 7.6.1.3 High Limit Register (address = 02h) [Factory default reset = 6000h]
- 7.6.1.4 Low Limit Register (address = 03h) [Factory default reset = 8000h]
- 7.6.1.5 EEPROM Unlock Register (address = 04h) [reset = 0000h]
- 7.6.1.6 EEPROM1 Register (address = 05h) [reset = XXXXh]
- 7.6.1.7 EEPROM2 Register (address = 06h) [reset = XXXXh]
- 7.6.1.8 EEPROM3 Register (address = 07h) [reset = 0000h]
- 7.6.1.9 EEPROM4 Register (address = 08h) [reset = XXXXh]
- 7.6.1.10 Device ID Register (address = 0Fh) [reset = 1116h]
- 7.6.1
Register Descriptions
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機(jī)械、封裝和可訂購(gòu)信息
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- DRV|6
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- DRV|6
訂購(gòu)信息
7.4.1.5 One-Shot Mode (OS)
When in shutdown mode, a single conversion can be performed by writing 11 to MOD bits in the configuration register, referred to as a one-shot conversion. After completing a one-shot conversion, the device returns to the low-power shutdown mode. A one-shot conversion cycle only consists of active conversion time and no standby period unlike CC mode. Thus, the duration of a one-shot conversion is only affected by the settings in the AVG bits. Figure 21 shows a timing diagram for this mode with an AVG setting of 00 and Figure 22 shows a timing diagram for this mode with an AVG setting of 01. At the end of a one-shot conversion, the Data_Ready flag in the configuration register is set. The Data_Ready flag is cleared by read of the configuration register or temperature result register. The state of the Data_Ready flag can also be monitored on the ALERT pin by setting the DR/nAlert_EN bit in the configuration register.
Figure 21. One-Shot Timing Diagram With No Averaging 
Figure 22. One-Shot Timing Diagram With 8 Averages