A. Open-Drain timing diagram assumes the RESET pin is
connected via an external pull-up resistor to VDD.
Figure 7-1 Timing Diagram for TLV841SxxL
(SENSE) Active Low Output [Open-Drain and
Push-Pull Output Topology]
A. Open-Drain timing diagram assumes the RESET pin is
connected via an external pull-up resistor to VDD.
Figure 7-2 Timing Diagram for TLV841SxxH
(SENSE) Active High Output [Open-Drain and
Push-Pull Output Topology]
A. Open-Drain timing diagram assumes the
RESET / RESET pin is connected via an external pull-up
resistor to VDD.
B. tD (no cap) is
included in tSTRT time delay. If tD delay is programmed by
an external capacitor connected to CT pin then tD programmed time
will be added to the startup time, VDD slew rate = 1 V / μs.
C. Be
advised that the VDD falling slew rate is (slew rate > 1 V / μs) and
resulting RESETin what is shown above figure. The
RESET behavior would be similar to #T5037184-71 if the slew
rate was much slower or if VDD decay time is larger than the prop delay
(tD_HL).
Figure 7-3 Timing Diagram for TLV841CxxL
(CT) Active Low Output [Open-Drain and Push-Pull
Output Topology]
A. Open-Drain timing diagram assumes the
RESET / RESET pin is connected via an external pull-up
resistor to VDD.
Figure 7-4 Timing Diagram for TLV841MxxL
Active Low Output (MR)
[Open-Drain and Push-Pull Output Topology]