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ZHCSHY2 March 2018 TLV320ADC3100

PRODUCTION DATA.

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8.3.5.2 Left-Justified Mode

In left-justified mode, the MSB of the right channel is valid on the rising edge of the bit clock following the falling edge of the word clock. Similarly, the MSB of the left channel is valid on the rising edge of the bit clock following the rising edge of the word clock. Figure 13 shows the standard timing of the left-justified mode.

Figure 13. Left-Justified Mode (Standard Timing)

Figure 14 shows the left-justified mode with Ch_Offset_1 = 1.

Figure 14. Left-Justified Mode With Ch_Offset_1 = 1

Figure 15 shows the left-justified mode with Ch_Offset_1 = 0 and bit clock inverted.

Figure 15. Left-Justified Mode With Ch_Offset_1 = 0, Bit Clock Inverted

For left-justified mode, the number of bit clocks per frame must be greater than twice the programmed word length of the data. Also, the programmed offset value must be less than the number of bit clocks per frame by at least the programmed word length of the data.

When the time-slot-based channel assignment is disabled (page 0, register 38, bit 0 = 0), the left and right channels have the same offset Ch_Offset_1 (page 0, register 28), and each edge of the word clock starts data transfer for one of the two channels, depending on whether or not channel swapping is enabled. Data bits are valid on the rising edges of the bit clock. With the time-slot-based channel assignment enabled (page 0, register 38, bit 0 = 1), the left and right channels have independent offsets (Ch_Offset_1 and Ch_Offset_2). The rising edge of the word clock starts data transfer for the first channel after a delay of its programmed offset (Ch_Offset_1) for this channel. Data transfer for the second channel starts after a delay of its programmed offset (Ch_Offset_2) from the LSB of the first-channel data. The falling edge of the word clock is not used.

With no channel swapping, the MSB of the left channel is valid on the (Ch_Offset_1 + 1)th rising edge of the bit clock following the rising edge of the word clock. Consequently, the MSB of the right channel is valid on the (Ch_Offset_1 + 1)th rising edge of the bit clock following the falling edge of the word clock. The timing diagram of Figure 14 illustrates the operation in this case, with an offset of 1. Because channel swapping is not enabled, the left-channel data are before the right-channel data. With channel swapping enabled, the MSB of the right channel is valid on the (Ch_Offset_1 + 1)th rising edge of the bit clock following the rising edge of the word clock. Thus, the MSB of the left channel is valid on the (Ch_Offset_1 + 1)th rising edge of the bit clock following the falling edge of the word clock. The timing diagram of Figure 16 depicts the operation in this case, with an offset of 1. As shown in the diagram, the right-channel data of a frame are before the left-channel data of that frame because of channel swapping. Otherwise, the behavior is similar to the case where channel swapping is disabled. The MSB of the right-channel data is valid on the second rising edge of the bit clock after the rising edge of the word clock, as a result of an offset of 1. Similarly, the MSB of the left-channel data is valid on the second rising edge of the bit clock after the falling edge of the word clock.

Figure 16. Left-Justified Mode With Ch_Offset_1 = 1, Channel Swapping Enabled

When the time-based-slot mode is enabled with no channel swapping, the MSB of the left channel is valid on the (Offset1 + 1)th rising edge of the bit clock following the rising edge of the word clock. Thus, the MSB of the right channel is valid on the (Ch_Offset_2 + 1)th rising edge of the bit clock following the LSB of the left channel.

Figure 17 shows the operation with time-based-slot mode enabled, Ch_Offset_1 = 0, and Ch_Offset_2 = 1. The MSB of the left channel is valid on the first rising edge of the bit clock after the rising edge of the word clock. Data transfer for the right channel does not wait for the falling edge of the word clock, and the MSB of the right channel is valid on the second rising edge of the bit clock after the LSB of the left channel.

Figure 17. Left-Justified Mode, Time-Based-Slot Mode Enabled, Ch_Offset_1 = 0, Ch_Offset_2 = 1

When the time-based-slot mode is enabled and channel swapping is enabled, the MSB of the right channel is valid on the (Ch_Offset_1 + 1)th rising edge of the bit clock following the rising edge of the word clock. Thus, the MSB of the left channel is valid on the (Ch_Offset_2 + 1)th rising edge of the bit clock following the LSB of the right channel. Figure 18 illustrates the operation in this mode with Ch_Offset_1 = 0 and Ch_Offset_2 = 1. The MSB of the right channel is valid on the first rising edge of the bit clock after the rising edge of the word clock. Data transfer for the left channel starts following the completion of data transfer for the right channel without waiting for the falling edge of the word clock. The MSB of the left channel is valid on the second rising edge of the bit clock after the LSB of the right channel.

Figure 18. Left-Justified Mode, Time-Based-Slot Mode Enabled, Ch_Offset_1 = 0, Ch_Offset_2 = 1,
Channel Swapping Enabled

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訂購信息

8.3.5.2 Left-Justified Mode