ZHCSHY2 March 2018 TLV320ADC3100
PRODUCTION DATA.
The TLV320ADC3100 supports the following standard audio sampling rates: 8 kHz, 11.025 kHz, 12 kHz, 16 kHz, 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, and 96 kHz. The converters can also operate at different sampling rates in various combinations, as described in this section.
The TLV320ADC3100 supports a wide range of options for generating clocks for the ADC section as well as the digital interface section and the other control blocks; see Figure 27. The ADC clocks require a source reference clock. The clock can be provided on the device pins MCLK and BCLK. The source reference clock for the ADC section can be chosen by programming the ADC_CLKIN value on page 0, register 4, bits 1:0. The ADC_CLKIN can then be routed through highly flexible clock dividers (see Figure 27) to generate various clocks required for the ADC and programmable digital filter sections. In the event that the desired audio or programmable digital filter clocks cannot be generated from the external reference clocks on MCLK and BCLK, the TLV320ADC3100 also provides the option of using an on-chip PLL that supports a wide range of fractional multiplication values to generate the required system clocks. Starting from ADC_CLKIN, the TLV320ADC3100 provides several programmable clock dividers to support a variety of sampling rates for the ADC and the clocks for the programmable digital filter section.