ZHCSHY2 March 2018 TLV320ADC3100
PRODUCTION DATA.
| IOVDD = 1.8 V | IOVDD = 3.3 V | UNIT | ||||
|---|---|---|---|---|---|---|
| MIN | MAX | MIN | MAX | |||
| tH(BCLK) | BCLK high period | 35 | 35 | ns | ||
| tL(BCLK) | BCLK low period | 35 | 35 | ns | ||
| ts(WS) | BCLK, WCLK setup time | 10 | 8 | ns | ||
| th(WS) | BCLK, WCLK hold time | 10 | 8 | ns | ||
| td(DO-BCLK) | BCLK to DOUT delay time | 25 | 20 | ns | ||
| tr | Rise time | 15 | 8 | ns | ||
| tf | Fall time | 15 | 8 | ns | ||
Figure 1. I2S, LJF, RJF Timing in Master Mode
Figure 2. DSP Timing in Master Mode
Figure 3. I2S, LJF, RJF Timing in Slave Mode
NOTE:
The WCLK falling edge is arbitrary inside a frame.