ZHCSOZ3 September 2021 TLIN1024A-Q1
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 說明（續）
- 6 Pin Configuration and Functions
- 7 Specifications
- 8 Parameter Measurement Information
-
9 Detailed Description
- 9.1 Overview
- 9.2 Functional Block Diagram
- 9.3
Feature Description
- 9.3.1 LIN (Local Interconnect Network) Bus
- 9.3.2 TXD (Transmit Input and Output)
- 9.3.3 RXD (Receive Output)
- 9.3.4 VSUP1/2 (Supply Voltage)
- 9.3.5 GND1/2 (Ground)
- 9.3.6 EN (Enable Input)
- 9.3.7 Protection Features
- 9.3.8 TXD Dominant Time Out (DTO)
- 9.3.9 Bus Stuck Dominant System Fault: False Wake-Up Lockout
- 9.3.10 Thermal Shutdown
- 9.3.11 Under Voltage on VSUP
- 9.3.12 Unpowered Device and LIN Bus
- 9.4 Device Functional Modes
- 10Application and Implementation
- 11Power Supply Recommendations
- 12Layout
- 13Device and Documentation Support
- 14Mechanical, Packaging, and Orderable Information
8 Parameter Measurement Information
Figure 8-1 Test System: Operating Voltage
Range with RX and TX Access
Figure 8-2 RX Response: Operating Voltage
Range
Figure 8-3 LIN Bus Input Signal
Figure 8-4 LIN Receiver Test with RX
Access
Figure 8-5 VSUP_NON_OP
Figure 8-6 Test Circuit for
IBUS_PAS_dom; TXD = Recessive State VBUS = 0 V
Figure 8-7 Test Circuit for
IBUS_PAS_rec
Figure 8-8 Test Circuit for
IBUS_NO_GND Loss of GND
Figure 8-9 Test Circuit for
IBUS_NO_BAT Loss of Battery
Figure 8-10 Test Circuit Slope Control and
Duty Cycle
Figure 8-11 Definition of Bus Timing
Parameters
Figure 8-12 Propagation Delay Test
Circuit
Figure 8-13 Propagation Delay
Figure 8-14 Mode Transitions
Figure 8-15 Wake-Up Through EN 
Figure 8-16 Wake-Up Through LIN