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ZHCSQV1C March 2020 – December 2022 TCAN1463-Q1

PRODUCTION DATA

封裝選項

機械數據 (封裝 | 引腳)

DYY|14
- MPSS114C
DMT|14
- MPSS087B
D|14
- MPDS177H

散熱焊盤機械數據 (封裝 | 引腳)

DMT|14
- QFND638

訂購信息

10.1.6.1 Layout Guidelines

The layout example provides information on components around the device. Place the protection and filtering circuitry as close to the bus connector, J1, to prevent transients, ESD and noise from propagating onto the board. Transient voltage suppression (TVS) device can be added for extra protection, shown as D1. The production solution can be either a bi-directional TVS diode or varistor with ratings matching the application requirements. This example also shows optional bus filter capacitors C6 and C7. A series common-mode choke (CMC) is placed on the CANH and CANL lines between the device and connector J1.

Design the bus protection components in the direction of the signal path. Do not force the transient current to divert from the signal path to reach the protection device. Use supply and ground planes to provide low inductance. Note that high-frequency currents follow the path of least impedance and not the path of least resistance. Use at least two vias for supply and ground connections of bypass capacitors and protection devices to minimize trace and via inductance.

Bypass and bulk capacitors should be placed as close as possible to the supply terminals of transceiver, examples are C1 on V_CC, C2 on V_IO, and C3 and C4 on the V_SUP supply.
V_IO pin of the transceiver is connected to the microcontroller IO supply voltage 'μC V'.
Bus termination: this layout example shows split termination. This is where the termination is split into two resistors, R3 and R4, with the center or split tap of the termination connected to ground via capacitor C5. Split termination provides common-mode filtering for the bus. When bus termination is placed on the board instead of directly on the bus, additional care must be taken to make sure the terminating node is not removed from the bus thus also removing the termination.
INH, pin 7, can have a 100 kΩ resistor (R1) to ground.
WAKE, pin 9, can recognize either a rising or a falling edge of a wake signal and is usually connected to an external switch. It should be configured as shown with C8 which is a 22 nF capacitor to GND where R5 is 33 kΩ and R6 is 3 kΩ.