ZHCSQV1C March 2020 – December 2022 TCAN1463-Q1
PRODUCTION DATA
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 Revision History
- 5 說明（續(xù)）
- 6 Pin Configuration and Functions
-
7 Specifications
- 7.1 Absolute Maximum Ratings
- 7.2 ESD Ratings
- 7.3 ESD Ratings - IEC Specifications
- 7.4 Recommended Operating Conditions
- 7.5 Thermal Information
- 7.6 Power Dissipation Ratings
- 7.7 Power Supply Characteristics
- 7.8 Electrical Characteristics
- 7.9 Timing Requirements
- 7.10 Switching Characteristics
- 7.11 Typical Characteristics
- 8 Parameter Measurement Information
-
9 Detailed Description
- 9.1 Overview
- 9.2 Functional Block Diagram
- 9.3
Feature Description
- 9.3.1 Supply Pins
- 9.3.2 Digital Inputs and Outputs
- 9.3.3 GND
- 9.3.4 INH Pin
- 9.3.5 WAKE Pin
- 9.3.6 CAN Bus Pins
- 9.3.7
Faults
- 9.3.7.1
Internal and External Fault Indicators
- 9.3.7.1.1 Power-Up (PWRON Flag)
- 9.3.7.1.2 Wake-Up Request (WAKERQ Flag)
- 9.3.7.1.3 Undervoltage Faults
- 9.3.7.1.4 CAN Bus Fault (CBF Flag)
- 9.3.7.1.5 TXD Clamped Low (TXDCLP Flag)
- 9.3.7.1.6 TXD Dominant State Timeout (TXDDTO Flag)
- 9.3.7.1.7 TXD Shorted to RXD Fault (TXDRXD Flag)
- 9.3.7.1.8 CAN Bus Dominant Fault (CANDOM Flag)
- 9.3.7.1
Internal and External Fault Indicators
- 9.3.8 Local Faults
- 9.4 Device Functional Modes
- 10Application Information Disclaimer
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
- DMT|14
訂購信息
9.3.8.2 TXD Dominant Timeout (TXD DTO)
While the CAN driver is in active mode a TXD dominant state timeout circuit prevents the local node from blocking network communication in event of a hardware or software failure where TXD is held dominant longer than the timeout period, t > tTXDDTO. The TXD dominant state timeout circuit is triggered by a falling edge on the TXD pin. If no rising edge is seen before on TXD before t > tTXDDTO than the CAN driver is disabled releasing the bus lines to the recessive level. This keeps the bus free for communication between other nodes on the network.
The CAN driver will be activated again on the next dominant-to-recessive transition on the TXD pin. During a TXDDTO fault the high-speed receiver remains active and the RXD output pin will mirror the CAN bus.
Figure 9-5 Timing Diagram for TXD DTOThe minimum dominant TXD time allowed by the dominant state timeout circuit limits the minimum possible transmitted data rate of the transceiver. The CAN protocol allows a maximum of eleven successive dominant bits to be transmitted in the worst case, where five successive dominant bits are followed immediately by an error frame. The minimum transmitted data rate may be calculated using the minimum tTXDDTO time in Equation 1.