ZHCS616E March 2012 – February 2017 TCA9554
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Parameter Measurement Information
- 8 Detailed Description
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12器件和文檔支持
- 13機械、封裝和可訂購信息
封裝選項
機械數據 (封裝 | 引腳)
散熱焊盤機械數據 (封裝 | 引腳)
- DW|16
訂購信息
10.1 Power-On Reset Requirements
In the event of a glitch or data corruption, the TCA9554 can be reset to its default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application.
The power-on reset is shown in Figure 31.
Figure 31. VCC is Lowered Below the POR Threshold, Then Ramped Back Up to VCCTable 8 specifies the performance of the power-on reset feature for the TCA9554.
Table 8. Recommended Supply Sequencing and Ramp Rates(1)
| PARAMETER | MIN | MAX | UNIT | ||
|---|---|---|---|---|---|
| VCC_FT | Fall rate | See Figure 31 | 1 | 2000 | ms |
| VCC_RT | Rise rate | See Figure 31 | 0.1 | 2000 | ms |
| VCC_TRR | Time to re-ramp (when VCC drops to VPOR_MIN – 50 mV or when VCC drops to GND) | See Figure 31 | 2 | μs | |
| VCC_GH | Level that VCCP can glitch down to, but not cause a functional disruption when VCC_GW = 1 µs | See Figure 32 | 1.2 | V | |
| VCC_MV | The minimum voltage that VCC can glitch down to without causing a reset (VCC_GH must not be violated) | See Figure 32 | 1.5 | V | |
| VCC_GW | Glitch width that does not cause a functional disruption when VCC_GH = 0.5 × VCC | See Figure 32 | 10 | μs | |
Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width (VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and device impedance are factors that affect power-on reset performance. Figure 32 and Table 8 provide more information on how to measure these specifications.
VPORR is critical to the power-on reset. VPORR is the voltage level at which the reset condition is released and all the registers and the I2C/SMBus state machine are initialized to their default states. The value of power-on-reset voltage differs based on the VCC being lowered to or from 0 (VPORR or VPORF). Figure 33 and Table 8 provide more details on this specification.
Figure 33. Waveform Describing VCC Voltage Level at Which Power-On-Reset (POR) Occurs