ZHCSHL6B September 2017 – November 2019 TAS5760M-Q1
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Digital I/O Pins
- 6.6 Master Clock
- 6.7 Serial Audio Port
- 6.8 Protection Circuitry
- 6.9 Speaker Amplifier in All Modes
- 6.10 Speaker Amplifier in Stereo Bridge Tied Load (BTL) Mode
- 6.11 Speaker Amplifier in Mono Parallel Bridge Tied Load (PBTL) Mode
- 6.12 I²C Control Port
- 6.13 Typical Idle, Mute, Shutdown, Operational Power Consumption
- 6.14 Typical Characteristics (Stereo BTL Mode): fSPK_AMP = 384 kHz
- 6.15 Typical Characteristics (Stereo BTL Mode): fSPK_AMP = 768 kHz
- 6.16 Typical Characteristics (Mono PBTL Mode): fSPK_AMP = 384 kHz
- 6.17 Typical Characteristics (Mono PBTL Mode): fSPK_AMP = 768 kHz
- 7 Parameter Measurement Information
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3 Feature Description
- 8.4
Device Functional Modes
- 8.4.1
Hardware Control Mode
- 8.4.1.1 Speaker Amplifier Shut Down (SPK_SD Pin)
- 8.4.1.2 Serial Audio Port in Hardware Control Mode
- 8.4.1.3 Soft Clipper Control (SFT_CLIP Pin)
- 8.4.1.4 Speaker Amplifier Switching Frequency Select (FREQ/SDA Pin)
- 8.4.1.5 Parallel Bridge Tied Load Mode Select (PBTL/SCL Pin)
- 8.4.1.6 Speaker Amplifier Sleep Enable (SPK_SLEEP/ADR Pin)
- 8.4.1.7 Speaker Amplifier Gain Select (SPK_GAIN [1:0] Pins)
- 8.4.1.8 Considerations for Setting the Speaker Amplifier Gain Structure
- 8.4.2 Software Control Mode
- 8.4.1
Hardware Control Mode
- 8.5
Register Maps
- 8.5.1 Control Port Registers - Quick Reference
- 8.5.2
Control Port Registers - Detailed Description
- 8.5.2.1 Device Identification Register (0x00)
- 8.5.2.2 Power Control Register (0x01)
- 8.5.2.3 Digital Control Register (0x02)
- 8.5.2.4 Volume Control Configuration Register (0x03)
- 8.5.2.5 Left Channel Volume Control Register (0x04)
- 8.5.2.6 Right Channel Volume Control Register (0x05)
- 8.5.2.7 Analog Control Register (0x06)
- 8.5.2.8 Reserved Register (0x07)
- 8.5.2.9 Fault Configuration and Error Status Register (0x08)
- 8.5.2.10 Reserved Controls (9 / 0x09) - (15 / 0x0F)
- 8.5.2.11 Digital Clipper Control 2 Register (0x10)
- 8.5.2.12 Digital Clipper Control 1 Register (0x11)
-
9 Application and Implementation
- 9.1 Application Information
- 9.2
Typical Applications
- 9.2.1 Stereo BTL Using Software Control, 32-Pin DAP Package Option
- 9.2.2 Stereo BTL Using Hardware Control, 32-Pin DAP Package Option
- 9.2.3 Mono PBTL Using Software Control, 32-Pin DAP Package Option
- 9.2.4 Mono PBTL Using Hardware Control, 32-Pin DAP Package Option
- 10Power Supply Recommendations
- 11Layout
- 12器件和文檔支持
- 13機械、封裝和可訂購信息
8.3.2.4 Digital Clipper
A digital clipper is integrated in the oversampled domain to provide a component-free method to set the clip point of the speaker amplifier. Through the "Digital Clipper Level x" controls in the I²C control port, the point at which the oversampled digital path clips can be set directly, which in turns sets the 10% THD+N operating point of the amplifier. This is useful for applications in which a single system is designed for use in several end applications that have different power rating specifications. Its place in the oversampled domain ensures that the digital clipper is acoustically appealing and reduces or eliminates tones which would otherwise foldback into the audio band during clipping events. Figure 43 shows a block diagram of the digital clipper.
Figure 43. Digital Clipper Simplified Block Diagram As mentioned previously, the audio signature of the amplifier when the digital clipper is active is very smooth, owing to its place in the signal chain. Figure 44 shows the typical behavior of the clipping events.
Figure 44. Digital Clipper Example Waveform for Various Settings of Digital Clip Level [19:0] It is important to note that the actual signal developed across the speaker will be determined not only by the digital clipper, but also the analog gain of the amplifier. Depending on the analog gain settings and the PVDD level applied, clipping could occur as a result of the voltage swing that is determined by the gain being larger than the available PVDD supply rail. The gain structures are discussed in detail below for both Hardware Control Mode and Software Control Mode.