ZHCSTS0F October 1993 – November 2023 SN65LBC173 , SN75LBC173
PRODUCTION DATA
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
Figure 4-1 D or N Package| PIN | TYPE(1) | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| 1B | 1 | I | Channel 1 Inverting Differential Input |
| 1A | 2 | I | Channel 1 Non-Inverting Differential Input |
| 1Y | 3 | O | Channel 1 Output |
| G | 4 | I | Active High Receiver Enable |
| 2Y | 5 | O | Channel 2 Output |
| 2A | 6 | I | Channel 2 Non-Inverting Differential Input |
| 2B | 7 | I | Channel 2 Inverting Differential Input |
| GND | 8 | GND | Device Ground |
| 3B | 9 | I | Channel 3 Inverting Differential Input |
| 3A | 10 | I | Channel 3 Non-Inverting Differential Input |
| 3Y | 11 | O | Channel 3 Output |
| G | 12 | I | Active Low Receiver Enable |
| 4Y | 13 | O | Channel 4 Output |
| 4A | 14 | I | Channel 4 Non-Inverting Differential Input |
| 4B | 15 | I | Channel 4 Inverting Differential Input |
| VCC | 16 | POW | Device Supply |